Texas Instruments Jacinto 7 DRA829 - Page 41

Resource
nRSTOUT_SOC TPS65941213-Q1
PMIC Delay Diagram Total Delay Rail Name
0 us H_SOC_PORz_1V8
nRSTOUT_SOC TPS65941213-Q1 200 us H_SOC_PORz_1V8
Figure 6-5. ESM_SOC_ERROR Sequence
6.3.5 PWR_SOC_ERROR
In the event of an error on any of the power rails which are part of the SOC power rail group, the
PWR_SOC_ERROR sequence is performed. The nRSTOUT_SOC pin is pulled low and the SOC power rails
execute a normal processor power down sequence except the MCU power group remains energized as shown
in Figure 6-6. The state of the I2C_7 trigger in both PMICs determines whether the DDR supplies and control
signal remain energized (I2C_7=1) or disabled (I2C_7=0), as shown in Figure 6-7.
In the start of the sequence the following instructions are executed:
// TPS65941213
// Set AMUXOUT_EN and CLKMON_EN, clear LPM_EN and nRSTOUT_SOC
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x18 MASK=0xE1
// Clear SPMI_LPM_EN
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF
//TPS65941111
// Set AMUXOUT_EN and CLKMON_EN, clear LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x18 MASK=0xE3
// Clear SPMI_LPM_EN
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF
Resource PMIC Delay Diagram Total Delay Rail Name
nRSTOUT_SOC TPS65941213-Q1
0 us H_SOC_PORz_1V8
LDO3 TPS65941213-Q1 2500 us VDD_DLL_0V8
BUCK123 TPS65941213-Q1 2500 us VDD_CPU(AVS)
BUCK5 TPS65941213-Q1 3000 us VDD_PHY_1V8
BUCK5 TPS65941111-Q1 500 us VDD_RAM_0V85
LDO3 TPS65941111-Q1 500 us VDD_IO_1V8
BUCK1234 TPS65941111-Q1 2500 us VDD_CORE_0V8
LDO4 TPS65941111-Q1
3000 us VDA_PLL_1V8
LDO1 TPS65941111-Q1 3500 us VDD_SD_DV
LDO2 TPS65941111-Q1 3500 us VDD_USB_3V3
Figure 6-6. PWR_SOC_ERROR with I2C_7 High in both PMICs
www.ti.com Pre-Configurable Finite State Machine (PFSM) Settings
SLVUC99 – JANUARY 2022
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Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto
™
7 DRA829 or
TDA4VM Automotive PDN-0C
41
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