Table 3-1 identifies which power resources are required to support different system features. In the Active SoC
column, there is an additional option for including or excluding the VPP_x(EFUSE) rail. LDO1 and LDO2 of
TPS65941111, which support optional SD CARD and USB Interface features, are enabled as part of the power
on sequence as shown in Figure 6-11. Even if these System Features are not used, the regulators are energized
as part of the power up sequence.
Table 3-1. PDN Power Mapping and System Features
Power Mapping System Features
(1)
Device
Power
Resource
Power Rails
Processor and Memory
Domains
Active SoC MCU - only
DDR
Retention
SD Card
USB
Interface
TPS659412
13-Q1
BUCK123
VDD_CPU_
AVS
VDD_CPU R
FB_B3 VDDSHVx_MCU (3.3 V) R R
BUCK4
VDD_MCU_
0V85
VDDAR_MCU, VDD_MCU R R
BUCK5
VDD_PHY_
1V8
VDDA_1P8_PHYs R
LDO1
VDD1_DDR
_1V8
Mem: VDD1 R O
(2)
R
(2)
LDO2
VDD_MCUI
O_1V8
VDDSHVx_MCU (1.8 V)
R R
Mem: VCC
LDO3
VDA_DLL_0
V8
VDDA_0P8_PLLs/DLLs R
LDO4
VDA_MCU_
1V8
VDDA_x R R
TPS659411
11-Q1
BUCK1234
VDD_CORE
_0V8
VDD_CORE,
VDDA_0P8_PHYs
R
BUCK5 VDD_RAM_
0V85
VDDAR_CPU/CORE R
LDO1
VDD_SD_D
V
VDDSHV5 R
LDO2
VDD_USB_
3V3
VDDA_3P3_USB R
LDO3
VDD_IO_1V
8
VDDS_MMC0
R
Mem: VCCQ
LDO4 VDA_PLL_1
V8
VDDA_1P8_PLLs R
TPS22965-
Q1
Load Switch
VDD_MCUI
O_3V3
VDDSHVx_MCU (3.3 V) R R
TPS22965-
Q1
Load Switch
VDD_IO_3V
3
VDDSHV0-4,VDDSHV6
(3.3 V)
R
TLV73318P-
Q1
LDO VPP_EFUS
E_1V8
VPP_x(EFUSE) O
TPS62813-
Q1
BUCK VDD_DDR_
1V1
VDDS_DDR_BIAS,
VDDS_DDR_IO
R O
(3)
R
(3)
Mem: VDD2
(1) 'R' is required and 'O' is optional.
(2) LDO1 of the TPS65941213-Q1 remains on when TRIGGER_I2C_7, in FSM_I2C_TRIGGERS Register, is set.
(3) The TPS62813-Q1 is controlled by the TPS65941111-Q1 GPIO3 and remains active while TRIGGER_I2C_7, in FSM_I2C_TRIGGERS,
is set.
Processor Connections www.ti.com
6 Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto
™
7 DRA829 or
TDA4VM Automotive PDN-0C
SLVUC99 – JANUARY 2022
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