CPU Vector Table
For TI silicon debug and test purposes the vectors located in the boot ROM memory point to locations in
the M0 SARAM block as described in Table 1-1 . During silicon debug, you can program the specified
locations in M0 with branch instructions to catch any vectors fetched from boot ROM. This is not required
for normal device operation.
Table 1-1. Vector Locations
Location in Contents Location in Contents
Vector Boot ROM (i.e., points to) Vector Boot ROM (i.e., points to)
RESET 0x3F FFC0 InitBoot (0x3F FB50) RTOSINT 0x3F FFE0 0x00 0060
INT1 0x3F FFC2 0x00 0042 Reserved 0x3F FFE2 0x00 0062
INT2 0x3F FFC4 0x00 0044 NMI 0x3F FFE4 0x00 0064
INT3 0x3F FFC6 0x00 0046 ILLEGAL
(1)
0x3F FFE6 0x00 0066 or ITRAPIsr
INT4 0x3F FFC8 0x00 0048 USER1 0x3F FFE8 0x00 0068
INT5 0x3F FFCA 0x00 004A USER2 0x3F FFEA 0x00 006A
INT6 0x3F FFCC 0x00 004C USER3 0x3F FFEC 0x00 006C
INT7 0x3F FFCE 0x00 004E USER4 0x3F FFEE 0x00 006E
INT8 0x3F FFD0 0x00 0050 USER5 0x3F FFF0 0x00 0070
INT9 0x3F FFD2 0x00 0052 USER6 0x3F FFF2 0x00 0072
INT10 0x3F FFD4 0x00 0054 USER7 0x3F FFF4 0x00 0074
INT11 0x3F FFD6 0x00 0056 USER8 0x3F FFF6 0x00 0076
INT12 0x3F FFD8 0x00 0058 USER9 0x3F FFF8 0x00 0078
INT13 0x3F FFDA 0x00 005A USER10 0x3F FFFA 0x00 007A
INT14 0x3F FFDC 0x00 005C USER11 0x3F FFFC 0x00 007C
DLOGINT 0x3F FFDE 0x00 005E USER12 0x3F FFFE 0x00 007E
(1)
As of version 4 of the boot ROM code, this vector points to a ITRAP interrupt service routine, ITRAPIsr(), within the boot ROM.
This ISR attempts to enable the watchdog and loops until the watchdog resets the part. On previous revisions, this vector points
to location 0x66 in M0 SARAM. Refer to Section 4.1 to determine the version of the boot ROM code on a particular device.
SPRU722C – November 2004 – Revised October 2006 Boot ROM Overview 15
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