4.1 Boot ROM Version and Checksum Information
4.2 Bootloader Code Revision History
Boot ROM Version and Checksum Information
The boot ROM contains its own version number located at address 0x3F FFBA. This version number
starts at 1 and will be incremented any time the boot ROM code is modified. The next address, 0x3F
FFBB contains the month and year (MM/YY in decimal) that the boot code was released. The next four
memory locations contain a checksum value for the boot ROM. Taking a 64-bit summation of all
addresses within the ROM, except for the checksum locations, generates this checksum.
Table 4-1. Bootloader Revision and Checksum
Information
Address Contents
0x3F FFB9 Flash API silicon compatibility check.
This location is read by some versions of
the flash API to make sure it is running
on a compatible silicon version.
0x3F FFBA Boot ROM Version Number
0x3F FFBB MM/YY of release (in decimal)
0x3F FFBC Least significant word of checksum
0x3F FFBD . . .
0x3F FFBE . . .
0x3F FFBF Most significant word of checksum
The following table shows the boot ROM revision per device. A revision history and code listing for the
latest boot ROM code can be found in Chapter 4 . In addition, a .zip file with each revision of the boot
ROM code can be downloaded from the TI website at the same location as this document.
Table 4-2. Bootloader Revision Per Device
Device(s) Silicon REVID Boot ROM Revision
(Address 0x883)
F2808, F2806, 0 (First silicon) Version 1
F2802, F2801
F2808, F2806, 1 (Rev A) Version 2
F2802, F2801
F2808, F2806, 2 (Rev B) and later Version 3
F2802, F2801
C2802, C2801 0 (First silicon) and Version 3
later
F2809 0 (First silicon) Version 4
F28044 0 (First silicon) Version 4
• Version 4, Released: April 2006
The following changes were made in V4:
– The ITRAP vector location in the CPU vector table was changed to point to an ITRAP interrupt
service routine located within the boot ROM. This ISR attempts to enable the watchdog and then
loops until the device resets. This vector will be used for any ITRAP that occurs after reset and
before the user initializes and enables the PIE vector table. In previous revisions of the boot ROM
code, this vector pointed to a memory location in M0 SARAM.
– The version number, release date and checksum memory locations have been updated to reflect
the new release.
• Version 3, Released: April 2005
The following changes were made in V3:
– The contents of the flash API silicon compatibility location (0x3F FFB9) was changed from 0xFFFF
56 Bootloader Code Overview SPRU722C – November 2004 – Revised October 2006
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