Bootloader Code Listing (V3.0)
// TI File $Revision: /main/4 $
// Checkin $Date: January 10, 2005 15:57:47 $
//###########################################################################
//
// FILE: I2C_Boot.c
//
// TITLE: 280x I2C Boot mode routines
//
// Functions:
//
// Uint32 I2C_Boot(void)
// inline void I2C_Init(void)
// inline Uint16 I2C_CheckKeyVal(void)
// inline void I2C_ReservedFn(void)
// Uint16 I2C_GetWord(void)
//
// Notes:
// The I2C code contained here is specifically streamlined for the F280x
// bootloader. It can be used to load code via the I2C port into the
// 280x RAM and jump to an entry point within that code.
//
// Features/Limitations:
// - The I2C boot loader code is written to communicate with an EEPROM
// device at address 0x50. The EEPROM must adhere to conventional I2C
// EEPROM protocol (see the boot rom documentation) with a 16-bit
// base address architecture (as opposed to 8-bits). The base address
// of the code should be contained at address 0x0000 in the EEPROM.
// - The input frequency to the F280x device must be between 14Mhz and
// 24Mhz, creating a 7Mhz to 12Mhz system clock. This is due to a
// requirement that the I2C clock be between 7Mhz and 12Mhz to meet all
// of the I2C specification timing requirements. The I2CPSC default value
// is hardcoded to 0 so that the I2C clock will not be divided down from
// the system clock. The I2CPSC value can be modified after receiving
// the first few bytes from the EEPROM (see the boot rom documentation),
// but it is advisable not to, as this can cause the I2C to operate out
// of specification with a system clock between 7Mhz and 12Mhz.
// - The bit period prescalers (I2CCLKH and I2CCLKL) are configured to
// run the I2C at 50% duty cycle at 100kHz bit rate (standard I2C mode)
// when the system clock is 12Mhz. These registers can be modified after
// receiving the first few bytes from the EEPROM (see the boot rom
// documentation). This allows the communication to be increased up to
// a 400kHz bit rate (fast I2C mode) during the remaining data reads.
// - Arbitration, bus busy, and slave signals are not checked. Therefore,
// no other master is allowed to control the bus during this
// initialization phase. If the application requires another master
// during I2C boot mode, that master must be configured to hold off
// sending any I2C messages until the F280x application software
// signals that it is past the bootloader portion of initialization.
// - The non-acknowledgement bit is only checked during the first message
// sent to initialize the EEPROM base address. This ensures that an
// EEPROM is present at address 0x50 before continuing on. If an EEPROM
// is not present, code will jump to the Flash entry point. The
// non-acknowledgement bit is not checked during the address phase of
// the data read messages (I2C_GetWord). If a non-acknowledge is
// received during the data read messages, the I2C bus will hang.
//
//###########################################################################
// $TI Release:$
// $Release Date:$
//###########################################################################
#include "DSP280x_Device.h" // DSP280x Headerfile Include File
#include "280x_Boot.h"
// Private functions
78 Bootloader Code Overview SPRU722C – November 2004 – Revised October 2006
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