Advisory (continued) PLL: May Not Lock on the First Lock Attempt
AUXPLL Workaround:
CPU Timer 2 can be used to detect that the AUXPLL is active before it is used as a clock
source for USB. If the AUXPLL is not active, repeat the lock attempt until successful.
The AUXPLLSTS[SLIPS] should also be checked immediately after setting the PLL as the
AUXPLLCLK source with AUXPLLCTL1[PLLCLKEN]. If SLIPS indicates a PLL slip, then
the PLL should be disabled and locked again until there are no slips detected.
See the C2000Ware InitAuxPll() function for an example implementation of this
workaround, as well as the DriverLib function SysCtl_setAuxClock().
Note
The USB Boot Mode does not implement the previous workarounds.
Applications using USB Boot will need to implement any retry attempts at the
system level.
Advisory PLL: Power Down and Bypass May Take up to 120 SYSCLK Cycles to be Effective
Revisions Affected
0, A, B, C
Details When the PLL is powered down (that is, SYPLLCTL1.PLLEN = 0) or bypassed (that
is, SYSPLLCTL1.PLLCLKEN = 0), there is a necessary period of clock synchronization
before the PLL bypass completes. During this time, if PLLSYSCLKDIV (or other clock
divider) is set to a smaller value, the resulting system clock could be unexpectedly more
than the rated device frequency.
Implementing the workaround below will allow the PLL bypass operation to complete
before any other code is executed, ensuring expected device frequencies and proper
system operation.
Workarounds Add a software delay of 120 SYSCLK cycles using a NOP instruction while performing
either a PLL power down or a PLL bypass operation.
Example:
SYSPLLCTL1.PLLCLKEN = 0; // Bypassing the PLL
asm(" RPT #120 || NOP"); // Delay of 120 SYSCLK Cycles
SYSPLLCTL1.PLLEN = 0; // Powering down the PLL
asm(" RPT #120 || NOP"); // Delay of 120 SYSCLK Cycles
The latest released C2000Ware, which has this workaround implemented, can be used as
reference.
Silicon Revision C Usage Notes and Advisories www.ti.com
18 TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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