Advisory SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and OSR
= 256
Revisions Affected
0, A, B, C
Details If the differential input of the Sigma-Delta Filter Module (SDFM) is greater than or equal
to +FSR (full-scale differential voltage input range), then the output of the SDFM clips with
a stream of ones. When this stream of ones is fed to a data filter that is configured as a
sinc3 filter with an OSR = 256, the output of the filter does not saturate at the maximum
value (16777215 in 32-bit mode or 32767 in 16-bit mode); but, instead roll over to the
minimum value (–16777216 in 32-bit mode or –32768 in 16-bit mode).
Workarounds Maintain the differential input of the SDFM in the specified linear input range as specified
in the modulator data sheet.
Advisory SDFM: Spurious Data Acknowledge Event When Data Filter is Configured and
Enabled for the First Time
Revisions Affected
0, A, B, C
Details When the SDFM data filter is configured and enabled for the first time, it is possible to get
one spurious data acknowledge event (AFx) before the data filter settles to give correct
digital data. Subsequent data acknowledge events (AFx)/DMA events occur correctly as
per data filter configuration.
Workarounds Do the following:
1. Configure and enable the SDFM data filter.
2. Delay for at least latency of data filter + 5 SD-Cx clock cycles.
3. Enable SDFM data acknowledge interrupts/DMA events.
Advisory SDFM: Spurious Data Acknowledge Event When Data Filter is Synchronized Using
PWM FILRES Signal
Revisions Affected
0, A, B, C
Details When the SDFM data filters are synchronized using the PWM FILRES signal, it is
possible to get a spurious data acknowledge event (AFx) before the data filter settles
to give correct digital data. Subsequent data acknowledge events (AFx) occur correctly as
per data filter configuration before the next PWM FILRES signal.
Workarounds Do the following:
1. Choose any PWMx to work in the same time base as the PWM that generates the
FILRES pulse.
2. PWMx should also interrupt the CPU/CLA at least 1.2 µs after the PWM FILRES
pulse gets applied in order to clear the SDIFLG register that may be set because of
the spurious data acknowledge event.
3. SDFM_CPUISR or SDFM_CLATask:
a. Collect the required number of samples, N, after the FILRES pulse.
b. If the number of samples is less than or equal to N, clear the SDIFLG register;
otherwise, do not clear the SDIFLG register to prevent further SDFM interrupts.
www.ti.com Silicon Revision C Usage Notes and Advisories
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
19
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