Advisory SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR)
Will Trigger Spurious Data Acknowledge Events
Revisions Affected
0, A, B, C
Details When SDFM data settings—such as filter type or DOSR settings—are dynamically
changed during run time, spurious data-filter-ready events will be triggered. The spurious
data-ready event will trigger a corresponding CPU interrupt, CLA task, and DMA trigger if
configured appropriately.
Workarounds When SDFM data filter settings need to be changed dynamically, follow the procedure
below to ensure spurious data-filter-ready events are not generated:
1. Disable the SDFM data filter.
2. Change SDFM data filter settings such as filter type or DOSR.
3. Delay for at least a latency of data filter + 5 SD-Cx clock cycles.
4. Enable the SDFM data filter.
Advisory SDFM: Manchester Mode (Mode 2) Does Not Produce Correct Filter Results Under
Several Conditions
Revisions Affected
0, A, B, C
Details The Manchester decoding algorithm samples the Manchester bitstream with SYSCLK
in a calibration window of 1024 SDx_Dy signal transitions. The derived clock from the
Manchester bitstream is used to sample for data in the subsequent calibration window
cycle.
There are several scenarios that can cause large errors in the filter results:
• Any single noise event on SDx_Dy can corrupt the decoded Manchester clock and
cause subsequent data to be sampled at an incorrect frequency.
• If the Manchester bitstream clock rate is a near exact integer multiple of SYSCLK,
then an occasional Manchester bit can be skipped when the phases of the Manchester
stream and internal SYSCLK drift past each other in phase before the next 1024
transition calibration window becomes effective. Deviations in duty cycle from 50% of
the Manchester clock also need to be accounted for to ensure the longer Manchester
pulses are not an integer multiple of SYSCLK. This situation can be unavoidable if the
clock sources for either the SD modulator or this device have a wide variation since a
wide range of keep out frequencies become problematic
• If the Manchester edge delay variation between rising and falling (duty cycle of the
bitstream) is greater than one SYSCLK, then the SDFM clock decode algorithm can
incorrectly identify the clock period as shorter than it is.
Workarounds The workarounds available are:
• Avoid using Manchester mode and consider using Mode 0, which provides the best
filter performance under noisy conditions. This is the recommended workaround.
• Avoid any noise on the Manchester bitstream and avoid integer multiples of SYSCLK
for the selected Manchester clock source. A precision clock source for the modulator
and this device must be used.
• Ensure rising and falling edge delays (high and low pulses) are within one SYSCLK of
each other in length.
• Design an application-level algorithm that is robust against occasional incorrect SDFM
results.
www.ti.com Silicon Revision C Usage Notes and Advisories
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
21
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