Advisory FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32 Instructions
Revisions Affected
0, A, B, C
Details This advisory applies to the EINVF32 and EISQRTF32 instructions. The expected results
for these instructions are correct; however, the underflow (LUF) and overflow (LVF) flags
are not. These flags are invalid and should not be used.
The LUF and LVF flags are not accessible using C code, so the overall impact of this
advisory is expected to be small. If the user chooses to use these flags (for example,
when coding a time-critical algorithm) in assembly as part of a mixed C/ASM project, the
user will need to disable interrupts around the assembly code using the flags, and also
preserve the flags through any use of EINVF32 or EISQRTF32 instructions.
Workarounds There is no workaround for using these flags in C code, and they should be considered
invalid for the reasons presented under NOTES ON COMPILER AND TOOLS USAGE.
The workaround shown here provides a way to preserve the LVF, LUF flags across the
use of EISQRTF32 and EINVF32 in assembly-only code.
Do not rely on the LUF and LVF flags to catch underflow/overflow conditions resulting
from the EINVF32 and EISQRTF32 instructions. Instead, check the operands for the
following conditions (in code) before using each instruction:
EINVF32 Divide by 0
EISQRTF32 Divide by 0, Divide by a negative input
Disregard the contents of the LUF and LVF flags by saving the flags to the stack
before calling the instruction, and subsequently restoring the values of the flags once
the instruction completes.
MOV32 *SP++,STF ; Save off current status flags
EISQRTF32/EINVF32 ; Execute operation
NOP ; Wait for operations to complete
MOV32 STF,*--SP ; Restore previous status flags
If the PIE interrupts are tied to the LUF and LVF flags, disable the interrupts (at the PIE)
before using either the EINVF32 or EISQRTF32 instruction. Check to see if the LUF and
LVF flags are set; if they are, a variable can be set to indicate that a false LUF/LVF
condition is detected. Clear the flags in the STF (FPU status flag) before re-enabling the
interrupts.
Once the interrupts are reenabled at the PIE, the interrupt may occur (if the LUF/LVF
interrupt lines were asserted by either of the two instructions) and execution branches to
the Interrupt Service Routine (ISR). Check the flag to determine if a false condition has
occurred; if it has, disregard the interrupt.
Do not clear the PIE IFR bits (that latch the LUF and LVF flags) directly because an
interrupt event on the same PIE group (PIE group 12) may inadvertently be missed.
www.ti.com Silicon Revision C Usage Notes and Advisories
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
25
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