Advisory (continued) FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32 Instructions
Here is an example:
_flag_LVFLUF_set .usect ".ebss",2,1,1
...
MOV32 *SP++,STF ; Save off current status flags
; Load the PieCtrlRegs page to the DP
MOVW DP, #_PieCtrlRegs.PIEIER12.all
; Zero out PIEIER12.7/8, i.e. disable LUF/LVF interrupts
AND @_PieCtrlRegs.PIEIER12.all, #0xFF3F
EISQRTF32/EINVF32 ; Execute operation
MOVL XAR3, #_flag_LVFLUF_set ; Wait for operation to complete
MOV32 *+XAR3[0], STF ; save STF to _flag_LVFLUF_set
AND *+XAR3[0], #0x3 ; mask everything but LUF/LVF
; Clear Latched overflow, underflow flag
SETFLG LUF=0, LVF=0
; Re-enable PIEIER12.7/8, i.e. re-enable the LUF/LVF interrupts
OR @_PieCtrlRegs.PIEIER12.all, #0x00C0
MOV32 STF,*--SP ; Restore previous status flags
In the ISR,
__interrupt void fpu32_luf_lvf_isr (void)
{
// Check the flag for whether the LUF, LVF flags set by
// either EISRTF32 or EINVF32
if((flag_LVFLUF_set & 0x3U) != 0U)
{
//Reset flag
flag_LVFLUF_set = 0U;
// Do Nothing
}
else
{
//If flag_LVFLUF_set was not set then this interrupt
// is the legitimate result of an overflow/underflow
// from an FPU operation (not EISQRTF32/EINVF32)
...
// Handle Overflow/Underflow condition
...
...
...
}
// Ack the interrupt and exit
}
Silicon Revision C Usage Notes and Advisories www.ti.com
26 TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
To Next Page
Loading...
