Advisory CMPSS: COMPxLATCH May Not Clear Properly Under Certain Conditions
Revisions Affected
0, A, B, C
Details The CMPSS latched path is designed to retain a tripped state within a local latch
(COMPxLATCH) until it is cleared by software (via COMPSTSCLR) or by PWMSYNC.
COMPxLATCH is set indirectly by the comparator output after the signal has been
digitized and qualified by the Digital Filter. The maximum latency expected for the
comparator output to reach COMPxLATCH may be expressed in CMPSS module clock
cycles as:
LATENCY = 1 + (1 x FILTER_PRESCALE) + (FILTER_THRESH x FILTER_PRESCALE)
When COMPxLATCH is cleared by software or by PWMSYNC, the latch itself is cleared
as desired, but the data path prior to COMPxLATCH may not reflect the comparator
output value for an additional LATENCY number of module clock cycles. If the Digital
Filter output resolves to a logical 1 when COMPxLATCH is cleared, the latch will be set
again on the following clock cycle.
Workarounds Allow the Digital Filter output to resolve to logical 0 before clearing COMPxLATCH.
If COMPxLATCH is cleared by software, the output state of the Digital Filter can be
confirmed through the COMPSTS register prior to clearing the latch. For instances where
a large LATENCY value produces intolerable delays, the filter FIFO may be flushed by
reinitializing the Digital Filter (via CTRIPxFILCTL).
If COMPxLATCH is cleared by PWMSYNC, the user application should be designed such
that the comparator trip condition is cleared at least LATENCY cycles before PWMSYNC
is generated.
Advisory CMPSS: Ramp Generator May Not Start Under Certain Conditions
Revisions Affected
0, A, B, C
Details The Ramp Generator is designed to produce a falling-ramp DAC reference that is
synchronized with a PWMSYNC signal. Upon receiving a PMWSYNC signal, the Ramp
Generator will start to decrement its DAC value. When COMPSTS[COMPHSTS] is
asserted by a trip event, the Ramp Generator will stop decrementing its DAC value.
If COMPSTS[COMPHSTS] is asserted simultaneously with a PWMSYNC signal, the
desired behavior is for the PWMSYNC signal to take priority such that the Ramp
Generator starts to decrement in the new EPWM cycle. Instead of the desired behavior,
the COMPSTS[COMPHSTS] trip condition will take priority over PWMSYNC such that the
Ramp Generator stops decrementing for a full EPWM cycle until the next PWMSYNC
signal is detected.
Workarounds Avoid COMPSTS[COMPHSTS] trip conditions when PWMSYNC is generated. For
example, peak current mode control applications can limit the PWM duty cycle to a
maximum value that will avoid simultaneous COMPSTS[COMPHSTS] and PWMSYNC
assertions.
www.ti.com Silicon Revision C Usage Notes and Advisories
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
35
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