Advisory SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang
Revisions Affected
0, A, B, C
Details When the CLKSRCCTL1 register is written more than once without delay between writes,
the system can hang and can only be recovered by an external XRS reset or Watchdog
reset. The occurrence of this condition depends on the clock ratio between SYSCLK and
the clock selected by OSCCLKSRCSEL, and may not occur every time.
If this issue is encountered while using the debugger, then after hitting pause, the program
counter will be at the Boot ROM reset vector.
Implementing the workaround will avoid this condition for any SYSCLK to OSCCLK ratio.
Workarounds Add a software delay of 300 SYSCLK cycles using an NOP instruction after every write to
the CLKSRCCTL1 register.
Example:
ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2
asm(" RPT #250 || NOP"); // Delay of 250 SYSCLK Cycles
asm(" RPT #50 || NOP"); // Delay of 50 SYSCLK Cycles
ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2
asm(" RPT #250 || NOP"); // Delay of 250 SYSCLK Cycles
asm(" RPT #50 || NOP"); // Delay of 50 SYSCLK Cycles
C2000Ware_3_00_00_00 and later revisions will have this workaround implemented.
Silicon Revision C Usage Notes and Advisories www.ti.com
34 TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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