Advisory During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the
FIFO Buffer
Revisions Affected
0, A, B, C
Details In DCAN FIFO mode, received messages with the same arbitration and mask IDs are
supposed to be placed in the FIFO in the order in which they are received. The CPU then
retrieves the received messages from the FIFO via the IF1/IF2 interface registers. Some
messages may be placed in the FIFO out of the order in which they were received. If the
order of the messages is critical to the application for processing, then this behavior will
prevent the proper use of the DCAN FIFO mode.
Workarounds None
www.ti.com Silicon Revision C Usage Notes and Advisories
SPRZ412M – DECEMBER 2013 – REVISED MARCH 2023
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TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Silicon
Revisions C, B, A, 0)
37
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