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11
SPRUI94–January 2017
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XDS110 Debug Probe
Table 2. Expansion Header Signal Mapping
Alternate Functions
Tiva
Pin
XDS110 Signal
Name
Pin Pin
XDS110 Signal
Name
Tiva Pin Alternate Functions
GPIO (PB5), ADC
(AIN11), I2C5 Data
120 ET_SSICLK 1 2 ET_PN0 107 GPIO (PN0)
GPIO (PB4), ADC
(AIN10), I2C5 Clock
121 ET_SSIFSS 3 4 ET_PN1 108 GPIO (PN1)
GPIO (PE4), ADC (AIN9) 123 ET_SSIDAT0 5 6 ET_PN2 109 GPIO (PN2)
GPIO (PE5), ADC (AIN8) 124 ET_SSIDAT1 7 8 ET_PN3 110 GPIO (PN3)
Ground GND 9 10 GND Ground
ADC (AIN1), GPIO (PE2) 13 ET_AIN1 11 12 ET_SCL 112 GPIO (PN5)
ADC (AIN2), GPIO (PE1) 14 ET_AIN2 13 14 ET_SDA 111 GPIO (PN4)
GPIO (PB0), CAN1 RX,
UART1 RX, I2C5 Clock
95 ET_PB0 15 16 ET_PM2 76
GPIO (PM3),
Timer3 CCP0
GPIO (PC4), UART7 RX 25 ET_PC4 17 18 ET_PH3 32 GPIO (PH3)
GPIO (PB1), CAN1 TX,
UART1 TX, I2C5 Data
96 ET_PB1 19 20 ET_PC5 27 GPIO (PC5), UART7 TX
POD_NON_ET
_VCC_SUPPLY
21 22
POD_NON_ET
_VCC_SUPPLY
DEBUG_TARGET
_VDD_IN
23 24
DEBUG_TARGET
_VDD_IN
Ground GND 25 26 GND Ground
Digital 3.3 V E3V3 27 28 E5V0 Digital 5 V
Digital 3.3 V E3V3 29 30 E5V0 Digital 5 V
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