ZED-F9T-Integration Manual
Port # Electrical interface
0x0000 DDC
(I²C
compatible)
0x0001 UART1
0x0102 UART2
0x0003 USB
0x0004 SPI
Table 16: Port number assignment reported in the UBX-MON-COMMS message.
3.3.11.1 UART ports
The serial ports consist of an RX and a TX line. Neither handshaking signals nor hardware flow
control signals are available. These serial ports operate in asynchronous mode. The baud rates can
be configured individually for each serial port. However, there is no support for setting different baud
rates for reception and transmission.
As of UBX protocol version 18 and beyond, the UART RX interface will be disabled when
more than 100 frame errors are detected during a one-second period. This can happen if the
wrong baud rate is used or the UART RX pin is grounded. An error message appears when
the UART RX interface is re-enabled at the end of the one-second period.
Baud rate Data bits Parity Stop bits
4800 8 none 1
9600 8 none 1
19200 8 none 1
38400 8 none 1
57600 8 none 1
115200 8 none 1
230400 8 none 1
460800 8 none 1
921600 8 none 1
Table 17: Possible UART interface configurations
Note that for protocols such as NMEA or UBX, it does not make sense to change the default word
length values (data bits) since these properties are defined by the protocol and not by the electrical
interface.
If the amount of data configured is too much for a certain port's bandwidth (e.g. all UBX messages
output on a UART port with a baud rate of 9600), the buffer will fill up. Once the buffer space is
exceeded, new messages to be sent will be dropped. To prevent message loss, the baud rate and
communication speed or the number of enabled messages should be carefully selected so that the
expected number of bytes can be transmitted in less than one second.
3.3.11.2 SPI port
SPI is a four-wire synchronous communication interface. In contrast to UART, the master provides
the clock signal, which therefore doesn't need to be specified for the slave in advance. Moreover, a
baud rate setting is not applicable for the slave.
CAUTION The SPI clock speed is limited depending on hardware and firmware versions!
3.3.11.2.1 Maximum SPI clock speed
The receiver supports a maximum SPI clock speed of 5.5 MHz.
3.3.11.2.2 Read access
As the register mode is not implemented for the SPI port, only the UBX/NMEA message stream is
provided. This stream is accessed using the back-to-back read and write access (see section back-
UBX-19005590 - R01
3 Receiver functionality Page 29 of 80
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