THEORY OF OPERATION
4-10
Versapulse Select Service Manual
0621-499-01 01/94
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Low Energy Attenuator Circuit - Operates and monitors the position of the low energy attenuator.
Described in subtopic 4.4.12.
DC Power Supply Voltage Monitoring Circuits - Monitors the +5, +15 and -15 VDC supply voltages.
Described in subtopic 4.4.13.
The safety processor provides independent monitoring of system operation and will disable system treatment
delivery if an abnormal condition is detected. It includes a 68000 microprocessor and its supporting circuits
(i.e., ROM, RAM, programmable timer, interrupt handling, clock, and µp bus support circuits) as well as an
ADC, digital I/O and NOFIRE circuit. The safety processor is described in subtopic 4.4.14.
4.4.2 Main Processor
Refer to 8-4. Motorola MC68000 microprocessor U32 reads/writes to its memory and I/O devices over a 20
bit address bus and 16 bit data bus. Y1 provides an 8 MHz clock input to the microprocessor. The 8 MHz
signal is also used as a clock input to the digital I/O chips (U43 and U44) and clock divider U33. The clock
divider provides 1 MHz output to the programmable timer U45 and a 2 MHz output used by the servo
controller U30.
At power up C61 begins charging through R89. After a short period the charge becomes sufficient to cause a
low to high transition at U24 pin 1, releasing to a high the /HALT/ and /RESET/ lines into the microproces-
sor - the microprocessor begins executing the software instructions stored in EPROM's U52 and U53. Press-
ing Reset Switch SW2 provides the same reset when the system is already on.
U25 will drive the /RESET/ line low if the 5 VDC supply voltage falls below ≈ 3 VDC. The /RST/ signal is
used to reset digital I/O chips U43 and U44, clock divider U33, and to set U65 to generate a delayed reset
signal (/RSTD/) to servo controller U30.
U54 and U55 provide 4K of 16 bit nonvolatile read/write memory to the Mµp. Data stored in this NVRAM
will be maintained even when power is removed.
U26 decodes the upper four bits of the address bus to enable the appropriate memory or memory mapped I/
O device. U56, U35, U34 U27, and U66 provide timing signals required to operate the address and data
buses.
U46 encodes interrupt requests from the programmable timer, UART controller, and Sµp (NOFIRE signal) for
input to the microprocessor. U51 provides interrupt acknowledge signals back to the I/O device requesting
an interrupt when the microprocessor is ready to handle the interrupt.
U57 detects bus errors, forcing the microprocessor to trap to an error handling routine if a bus cycle does not
complete within a set number of clocked "E" pulses.
Inputs from the vendor supplied DC power supply provide the Controller PCB with 5 VDC, 24 VDC, and ±
15 VDC through J5, as shown in the upper left corner of 8-5.
Programmable timer U45 (Refer to 8-5) provides timing functions for the main processor, including the
following:
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