THEORY OF OPERATION
4-24
Versapulse Select Service Manual
0621-499-01 01/94
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At turn on the coolant conductivity will tend to be higher, especially if the system has not been operated
recently, and then will decrease as the system coolant begins to circulate through the DI filter. Note that the
system software takes into account that the conductivity will be higher just after turn on, and then, if the DI
filter is operating properly, the conductivity will gradually drop.
The 70 Hz output of U17 leaves the CPU PCB at J4-2 and is routed to the coolant reservoir where the signal is
applied across a one cm gap in the coolant. The other side of the one cm gap is sensed at J4-1 (CONDUCTIV-
ITY SIGNAL), and input to transimpedence amplifier U17-14 . The output of U17-14 consists of positive and
negative pulses. The individual pulses are selected for input to the positive and negative inputs of U17-9 by
the action of U18-10 and U18-15 as driven by the oscillator U17-7 outputs (partly through U18-6). The output
of U17-8 (TP10) is 4 times the sensed conductivity in µS Siemens (e.g., a voltage of 3.5 volts at TP10 indicates a
sensed conductivity of 15 µS).
4.4.12 Low Energy Attenuator Circuit
The Low energy attenuator circuit inserts attenuation into the beam path to allow the Versapulse Select to
provide treatment pulse energies lower than the minimum pulse energy available out of the cavity.
The main processor asserts (high) the LPATTNDR signal to insert the attenuator. LPATTNDR is applied
through amplifier U40 (3/4) to opto-isolator U41. The U41 pin 8 output (24 VDC to insert) is connected to
Shutter PCB J11 -10, where it is applied to the base of Q4. Q4 on completes the ground return path for the 24
VDC supply to the solenoid that inserts the low power attenuator. The Low energy Solenoid is located on the
Single Solenoid PCB.
The Low Power Attenuator "normally open" signal (LPATNO) is the output of slotted optical switch LPT1 on
the Single Solenoid PCB.
When the switch is blocked, its sensed output is open. When the switch is not blocked its output is a ground.
The switch is blocked when the attenuator is energized, blocking the beam. The sensed line from LPT1 is sent
from the Single Solenoid PCB to the Shutter PCB, J17-11 to J14-11, then on to the Controller PCB, J11-11 to
CPU PCB J1-11. When the solenoid is energized, the service attenuator is in the beam path, LPT1 output is
open/ground, and Controller PCB U39-8 is forced high/low.
4.4.13 DC Power Supply Voltage Monitoring Circuits
Refer to 8-6. The main processor monitors the ±15 and +5 VDC power supply outputs through its ADC
circuit. The ± 15 VDC inputs are too large to be directly measured through the ADC, so both are divided
down to a lower level before input to the ADC MUX (U19). The -15 VDC is measured through voltage divider
R40/41 and inverting amplifier (gain is 1) as -15M (TP8). The +15 VDC is measured through voltage divider
RR38/39 as +15M. The +5 VDC is monitored directly, through R37 as +5M.
12/95
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