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Xilinx ML605 Hardware User's Guide
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ML605 Hardware User Gu
ide
www.xilinx.com
19
UG534 (v1.9) February 26, 2019
Detailed Des
cription
K12
DDR3_D6
16
DQ6
D11
DDR3_D7
18
DQ7
M13
DDR3_D8
21
DQ8
J14
DDR3_D9
23
DQ9
B13
DDR3_D10
33
DQ10
B12
DDR3_D11
35
DQ11
G10
DDR3_D12
22
DQ12
M11
DDR3_D13
24
DQ13
C12
DDR3_D14
34
DQ14
A11
DDR3_D15
36
DQ15
G11
DDR3_D16
39
DQ16
F11
DDR3_D17
41
DQ17
D14
DDR3_D18
51
DQ18
C14
DDR3_D19
53
DQ19
G12
DDR3_D20
40
DQ20
G13
DDR3_D21
42
DQ21
F14
DDR3_D22
50
DQ22
H14
DDR3_D23
52
DQ23
C19
DDR3_D24
57
DQ24
G20
DDR3_D25
59
DQ25
E19
DDR3_D26
67
DQ26
F20
DDR3_D27
69
DQ27
A20
DDR3_D28
56
DQ28
A21
DDR3_D29
58
DQ29
E22
DDR3_D30
68
DQ30
E23
DDR3_D31
70
DQ31
G21
DDR3_D32
129
DQ32
B21
DDR3_D33
131
DQ33
A23
DDR3_D34
141
DQ34
A24
DDR3_D35
143
DQ35
C20
DDR3_D36
130
DQ36
D20
DDR3_D37
132
DQ37
J20
DDR3_D38
140
DQ38
G22
DDR3_D39
142
DQ39
Table 1-4
:
DDR3 SODIMM Connections
(Cont’d)
U1 FPGA Pin
Schematic Net Name
J1 SODIMM
Pin Number
Pin Name
S
e
n
d
F
e
e
d
b
a
c
k
18
20
Table of Contents
Default Chapter
5
Table of Contents
5
Preface: about this Guide
7
Guide Contents
7
Additional Documentation
7
Additional Support Resources
8
Chapter 1: ML605 Evaluation Board
9
Overview
9
Additional Information
9
Features
10
Block Diagram
12
Related Xilinx Documents
12
Electrostatic Discharge Caution
13
Detailed Description
13
1 Virtex-6 XC6VLX240T-1FFG1156 FPGA
16
Configuration
16
I/O Voltage Rails
17
2 MB DDR3 Memory SODIMM
17
3 Mb Platform Flash XL
22
4 MB Linear BPI Flash
22
ML605 Flash Boot Options
23
5 System ACE CF and Compactflash Connector
27
6 Usb Jtag
29
7 Clock Generation
30
Oscillator (Differential)
30
Oscillator Socket (Single-Ended, 2.5V)
30
SMA Connectors (Differential)
32
8 Multi-Gigabit Transceivers (GTX Mgts)
34
9 PCI Express Endpoint Connectivity
35
10 SFP Module Connector
38
100 /1000 Tri-Speed Ethernet PHY
39
SGMII GTX Transceiver Clock Generation
40
12 USB-To-UART Bridge
42
13 USB Controller
43
506 DVI Codec
44
15 IIC Bus
45
Kb NV Memory
47
16 Status Leds
48
Ethernet PHY Status Leds
49
FPGA INIT and DONE Leds
50
17 User I/O
50
User Leds
51
User Pushbutton Switches
52
User DIP Switch
53
User SMA GPIO
54
LCD Display (16 Character X 2 Lines)
55
18 Switches
56
Power On/Off Slide Switch SW2
56
FPGA_PROG_B Pushbutton SW4 (Active-Low)
57
SYSACE_RESET_B Pushbutton SW3 (Active-Low)
57
System ACE CF Compactflash Image Select DIP Switch S1
58
Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2
59
19 VITA 57.1 FMC HPC Connector
60
20 VITA 57.1 FMC LPC Connector
66
21 Power Management
68
AC Adapter and Input Power Jack/Switch
68
Onboard Power Regulation
69
22 System Monitor
72
Configuration Options
77
Appendix A: Default Switch and Jumper Settings
80
Appendix B: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout
83
Appendix C: Xilinx Design Constraints
83
Overview
83
Appendix D: Regulatory and Compliance Information
85
Declaration of Conformity
85
CE Directives
85
CE Standards
85
Electromagnetic Compatibility
85
Safety
86
Markings
86
Appendix E: References
87
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User Guide
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Manual
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Xilinx ML605 Specifications
General
Brand
Xilinx
Model
ML605
Category
Motherboard
Language
English
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