VCU1525 Acceleration Platform User Guide 24
UG1268 (v1.0) November 13, 2017 www.xilinx.com
Chapter 3: Board Component Descriptions
The VCU1525 clocking diagram is shown in Figure 3-3.
X-Ref Target - Figure 3-6
Figure 3-6: VCU1525 Clocking Diagram
U9
U44
BANK 63
DDR4 C0 I/F
AY37/AY38 GC QBC
U13AF
XCVU9PFSGD2104
CLK0
Q0
Q1
Q2
Q3
SYSCLK0_300_/P/N
SYSCLK1_300_P/N
SYSCLK2_300_P/N
SYSCLK3_300_P/N
CLK0
CLK1
CLK2
CLK3
300 MHz
156.25 MHz
90 MHz
33.33 MHz
Si5335A-B06201-GM
BANK 70
DDR4 C2 I/F
F32/E32 GC QBC
U13Z
XCVU9PFSGD2104
Si53340-B-GM
GTY BANK 231
QSFPO I/F
U13AL
REFCLK1
XCVU9PFSGD2104
REFCLK0
BANK 72
DDR4 C3 I/F
J16/H16 GC QBC
U13X
XCVU9PFSGD2104
BANK 64
GPI0 I/F
U13AE
XCVU9PFSGD2104
AW20/AW19 GC
AU19/AV1 GC
U43
CLK0
Q0
Q1
Q2
Q3
Si53340-B-GM
CLK0
CLK1
CLK2
CLK3
300 MHz
156.25 MHz
90 MHz
33.33 MHz
Si5335A-B06201-GM
GTY BANK 230
QSFP1 I/F
U13AK
REFCLK0
XCVU9PFSGD2104
REFCLK1
SYSCLK_300_P/N
QSFP0_CLOCK_P/N
NC
NC
156.250 MHz
DEFAULT
I2C ADDR. 0X5D
U14
Si570BAB000544DG
USER_SI570_CLOCK_P/N
NC
MGT_SI570_CLOCK0_P/N
MGT_SI570_CLOCK1_P/N
U12
MGT_SI570_CLOCK0_P/N
SI570_OUTPUT_P/N
NC
QSFP1_CLOCK_P/N
NC
NC
X19970-103017