Xilinx VCU1525

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VCU1525 Acceleration Platform User Guide 48

UG1268 (v1.0) November 13, 2017 www.xilinx.com

Appendix A: Master Constraints File Listing

# MGT_SI570_CLOCK

set_property PACKAGE_PIN M10 [get_ports MGT_SI570_CLOCK0_C_N];

set_property IOSTANDARD LVDS [get_ports MGT_SI570_CLOCK0_C_N];

set_property PACKAGE_PIN M11 [get_ports MGT_SI570_CLOCK0_C_P];

set_property IOSTANDARD LVDS [get_ports MGT_SI570_CLOCK0_C_P];

set_property PACKAGE_PIN T10 [get_ports MGT_SI570_CLOCK1_C_N];

set_property IOSTANDARD LVDS [get_ports MGT_SI570_CLOCK1_C_N];

set_property PACKAGE_PIN T11 [get_ports MGT_SI570_CLOCK1_C_P];

set_property IOSTANDARD LVDS [get_ports MGT_SI570_CLOCK1_C_P];

# QSFP0

set_property PACKAGE_PIN K10 [get_ports QSFP0_CLOCK_N];

set_property IOSTANDARD LVDS [get_ports QSFP0_CLOCK_N];

set_property PACKAGE_PIN K11 [get_ports QSFP0_CLOCK_P];

set_property IOSTANDARD LVDS [get_ports QSFP0_CLOCK_P];

# QSFP1

set_property PACKAGE_PIN P10 [get_ports QSFP1_CLOCK_N];

set_property IOSTANDARD LVDS [get_ports QSFP1_CLOCK_N];

set_property PACKAGE_PIN P11 [get_ports QSFP1_CLOCK_P];

set_property IOSTANDARD LVDS [get_ports QSFP1_CLOCK_P];

# DDR4 C0 DIMM I/F

set_property PACKAGE_PIN AT36 [get_ports DDR4_C0_ADR0];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR0];

set_property PACKAGE_PIN AV36 [get_ports DDR4_C0_ADR1];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR1];

set_property PACKAGE_PIN AV37 [get_ports DDR4_C0_ADR2];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR2];

set_property PACKAGE_PIN AW35 [get_ports DDR4_C0_ADR3];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR3];

set_property PACKAGE_PIN AW36 [get_ports DDR4_C0_ADR4];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR4];

set_property PACKAGE_PIN AY36 [get_ports DDR4_C0_ADR5];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR5];

set_property PACKAGE_PIN AY35 [get_ports DDR4_C0_ADR6];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR6];

set_property PACKAGE_PIN BA40 [get_ports DDR4_C0_ADR7];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR7];

set_property PACKAGE_PIN BA37 [get_ports DDR4_C0_ADR8];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR8];

set_property PACKAGE_PIN BB37 [get_ports DDR4_C0_ADR9];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR9];

set_property PACKAGE_PIN AR35 [get_ports DDR4_C0_ADR10];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR10];

set_property PACKAGE_PIN BA39 [get_ports DDR4_C0_ADR11];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR11];

set_property PACKAGE_PIN BB40 [get_ports DDR4_C0_ADR12];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR12];

set_property PACKAGE_PIN AN36 [get_ports DDR4_C0_ADR13];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR13];

set_property PACKAGE_PIN AP35 [get_ports DDR4_C0_ADR14];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR14];

set_property PACKAGE_PIN AP36 [get_ports DDR4_C0_ADR15];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR15];

set_property PACKAGE_PIN AR36 [get_ports DDR4_C0_ADR16];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR16];

set_property PACKAGE_PIN AN35 [get_ports DDR4_C0_ADR17];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ADR17];

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