Xilinx VCU1525

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VCU1525 Acceleration Platform User Guide 49

UG1268 (v1.0) November 13, 2017 www.xilinx.com

Appendix A: Master Constraints File Listing

set_property PACKAGE_PIN AT35 [get_ports DDR4_C0_BA0];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_BA0];

set_property PACKAGE_PIN AT34 [get_ports DDR4_C0_BA1];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_BA1];

set_property PACKAGE_PIN BC37 [get_ports DDR4_C0_BG0];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_BG0];

set_property PACKAGE_PIN BC39 [get_ports DDR4_C0_BG1];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_BG1];

set_property PACKAGE_PIN AW38 [get_ports DDR4_C0_CK_C0];

set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4_C0_CK_C0];

set_property PACKAGE_PIN AV38 [get_ports DDR4_C0_CK_T0];

set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4_C0_CK_T0];

set_property PACKAGE_PIN BC38 [get_ports DDR4_C0_CKE0];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_CKE0];

set_property PACKAGE_PIN AU35 [get_ports DDR4_C0_CK_C1];

set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4_C0_CK_C1];

set_property PACKAGE_PIN AU34 [get_ports DDR4_C0_CK_T1];

set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4_C0_CK_T1];

set_property PACKAGE_PIN BC40 [get_ports DDR4_C0_CKE1];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_CKE1];

set_property PACKAGE_PIN AU36 [get_ports DDR4_C0_PAR];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_PAR];

set_property PACKAGE_PIN BB39 [get_ports DDR4_C0_ACT_B];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ACT_B];

set_property PACKAGE_PIN BA38 [get_ports DDR4_C0_ALERT_B];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ALERT_B];

set_property PACKAGE_PIN AT33 [get_ports DDR4_C0_EVENT_B];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_EVENT_B];

set_property PACKAGE_PIN AU31 [get_ports DDR4_C0_RESET_N];

set_property IOSTANDARD LVCMOS12 [get_ports DDR4_C0_RESET_N];

set_property PACKAGE_PIN AR33 [get_ports DDR4_C0_CS_B0];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_CS_B0];

set_property PACKAGE_PIN AP33 [get_ports DDR4_C0_CS_B1];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_CS_B1];

set_property PACKAGE_PIN AN33 [get_ports DDR4_C0_CS_B2];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_CS_B2];

set_property PACKAGE_PIN AM34 [get_ports DDR4_C0_CS_B3];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_CS_B3];

set_property PACKAGE_PIN AP34 [get_ports DDR4_C0_ODT0];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ODT0];

set_property PACKAGE_PIN AN34 [get_ports DDR4_C0_ODT1];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C0_ODT1];

set_property PACKAGE_PIN AW28 [get_ports DDR4_C0_DQ0];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ0];

set_property PACKAGE_PIN AW29 [get_ports DDR4_C0_DQ1];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ1];

set_property PACKAGE_PIN BA28 [get_ports DDR4_C0_DQ2];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ2];

set_property PACKAGE_PIN BA27 [get_ports DDR4_C0_DQ3];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ3];

set_property PACKAGE_PIN BB29 [get_ports DDR4_C0_DQ4];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ4];

set_property PACKAGE_PIN BA29 [get_ports DDR4_C0_DQ5];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ5];

set_property PACKAGE_PIN BC27 [get_ports DDR4_C0_DQ6];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ6];

set_property PACKAGE_PIN BB27 [get_ports DDR4_C0_DQ7];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ7];

set_property PACKAGE_PIN BE28 [get_ports DDR4_C0_DQ8];

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