Xilinx VCU1525

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VCU1525 Acceleration Platform User Guide 57

UG1268 (v1.0) November 13, 2017 www.xilinx.com

Appendix A: Master Constraints File Listing

set_property PACKAGE_PIN BE25 [get_ports DDR4_C1_DQ67];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C1_DQ67];

set_property PACKAGE_PIN BD23 [get_ports DDR4_C1_DQ68];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C1_DQ68];

set_property PACKAGE_PIN BC23 [get_ports DDR4_C1_DQ69];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C1_DQ69];

set_property PACKAGE_PIN BF23 [get_ports DDR4_C1_DQ70];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C1_DQ70];

set_property PACKAGE_PIN BE23 [get_ports DDR4_C1_DQ71];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C1_DQ71];

set_property PACKAGE_PIN BF9 [get_ports DDR4_C1_DQS_C0];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C0];

set_property PACKAGE_PIN BF10 [get_ports DDR4_C1_DQS_T0];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T0];

set_property PACKAGE_PIN AY15 [get_ports DDR4_C1_DQS_C1];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C1];

set_property PACKAGE_PIN AW15 [get_ports DDR4_C1_DQS_T1];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T1];

set_property PACKAGE_PIN BB10 [get_ports DDR4_C1_DQS_C2];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C2];

set_property PACKAGE_PIN BB11 [get_ports DDR4_C1_DQS_T2];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T2];

set_property PACKAGE_PIN AT13 [get_ports DDR4_C1_DQS_C3];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C3];

set_property PACKAGE_PIN AT14 [get_ports DDR4_C1_DQS_T3];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T3];

set_property PACKAGE_PIN BE11 [get_ports DDR4_C1_DQS_C4];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C4];

set_property PACKAGE_PIN BE12 [get_ports DDR4_C1_DQS_T4];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T4];

set_property PACKAGE_PIN BC12 [get_ports DDR4_C1_DQS_C5];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C5];

set_property PACKAGE_PIN BC13 [get_ports DDR4_C1_DQS_T5];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T5];

set_property PACKAGE_PIN AW18 [get_ports DDR4_C1_DQS_C6];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C6];

set_property PACKAGE_PIN AV18 [get_ports DDR4_C1_DQS_T6];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T6];

set_property PACKAGE_PIN AR16 [get_ports DDR4_C1_DQS_C7];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C7];

set_property PACKAGE_PIN AP16 [get_ports DDR4_C1_DQS_T7];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T7];

set_property PACKAGE_PIN BD24 [get_ports DDR4_C1_DQS_C8];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C8];

set_property PACKAGE_PIN BC24 [get_ports DDR4_C1_DQS_T8];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T8];

set_property PACKAGE_PIN BF8 [get_ports DDR4_C1_DQS_C9];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C9];

set_property PACKAGE_PIN BE8 [get_ports DDR4_C1_DQS_T9];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T9];

set_property PACKAGE_PIN AY12 [get_ports DDR4_C1_DQS_C10];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C10];

set_property PACKAGE_PIN AY13 [get_ports DDR4_C1_DQS_T10];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T10];

set_property PACKAGE_PIN BA9 [get_ports DDR4_C1_DQS_C11];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_C11];

set_property PACKAGE_PIN BA10 [get_ports DDR4_C1_DQS_T11];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C1_DQS_T11];

set_property PACKAGE_PIN AP14 [get_ports DDR4_C1_DQS_C12];

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