Name: Xilinx VCU1525
Brand: Xilinx
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VCU1525 Acceleration Platform User Guide 62

UG1268 (v1.0) November 13, 2017 www.xilinx.com

Appendix A: Master Constraints File Listing

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C2_DQ66];

set_property PACKAGE_PIN A38 [get_ports DDR4_C2_DQ67];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C2_DQ67];

set_property PACKAGE_PIN C39 [get_ports DDR4_C2_DQ68];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C2_DQ68];

set_property PACKAGE_PIN D39 [get_ports DDR4_C2_DQ69];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C2_DQ69];

set_property PACKAGE_PIN A40 [get_ports DDR4_C2_DQ70];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C2_DQ70];

set_property PACKAGE_PIN B40 [get_ports DDR4_C2_DQ71];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C2_DQ71];

set_property PACKAGE_PIN M26 [get_ports DDR4_C2_DQS_C0];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C0];

set_property PACKAGE_PIN N26 [get_ports DDR4_C2_DQS_T0];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T0];

set_property PACKAGE_PIN J26 [get_ports DDR4_C2_DQS_C1];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C1];

set_property PACKAGE_PIN J25 [get_ports DDR4_C2_DQS_T1];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T1];

set_property PACKAGE_PIN D30 [get_ports DDR4_C2_DQS_C2];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C2];

set_property PACKAGE_PIN D29 [get_ports DDR4_C2_DQS_T2];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T2];

set_property PACKAGE_PIN A28 [get_ports DDR4_C2_DQS_C3];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C3];

set_property PACKAGE_PIN A27 [get_ports DDR4_C2_DQS_T3];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T3];

set_property PACKAGE_PIN E40 [get_ports DDR4_C2_DQS_C4];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C4];

set_property PACKAGE_PIN E39 [get_ports DDR4_C2_DQS_T4];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T4];

set_property PACKAGE_PIN M31 [get_ports DDR4_C2_DQS_C5];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C5];

set_property PACKAGE_PIN N31 [get_ports DDR4_C2_DQS_T5];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T5];

set_property PACKAGE_PIN L36 [get_ports DDR4_C2_DQS_C6];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C6];

set_property PACKAGE_PIN L35 [get_ports DDR4_C2_DQS_T6];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T6];

set_property PACKAGE_PIN H38 [get_ports DDR4_C2_DQS_C7];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C7];

set_property PACKAGE_PIN J38 [get_ports DDR4_C2_DQS_T7];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T7];

set_property PACKAGE_PIN A39 [get_ports DDR4_C2_DQS_C8];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C8];

set_property PACKAGE_PIN B39 [get_ports DDR4_C2_DQS_T8];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T8];

set_property PACKAGE_PIN P28 [get_ports DDR4_C2_DQS_C9];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C9];

set_property PACKAGE_PIN R28 [get_ports DDR4_C2_DQS_T9];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T9];

set_property PACKAGE_PIN L28 [get_ports DDR4_C2_DQS_C10];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C10];

set_property PACKAGE_PIN M27 [get_ports DDR4_C2_DQS_T10];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T10];

set_property PACKAGE_PIN H27 [get_ports DDR4_C2_DQS_C11];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_C11];

set_property PACKAGE_PIN H26 [get_ports DDR4_C2_DQS_T11];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C2_DQS_T11];

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Brand	Xilinx
Model	VCU1525
Category	Microcontrollers
Language	English

Xilinx VCU1525 User Manual

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