Name: Xilinx VCU1525
Brand: Xilinx
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VCU1525 Acceleration Platform User Guide 64

UG1268 (v1.0) November 13, 2017 www.xilinx.com

Appendix A: Master Constraints File Listing

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_ADR16];

set_property PACKAGE_PIN G16 [get_ports DDR4_C3_ADR17];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_ADR17];

set_property PACKAGE_PIN J15 [get_ports DDR4_C3_BA0];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_BA0];

set_property PACKAGE_PIN H14 [get_ports DDR4_C3_BA1];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_BA1];

set_property PACKAGE_PIN D13 [get_ports DDR4_C3_BG0];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_BG0];

set_property PACKAGE_PIN J13 [get_ports DDR4_C3_BG1];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_BG1];

set_property PACKAGE_PIN L13 [get_ports DDR4_C3_CK_C0];

set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4_C3_CK_C0];

set_property PACKAGE_PIN L14 [get_ports DDR4_C3_CK_T0];

set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4_C3_CK_T0];

set_property PACKAGE_PIN K13 [get_ports DDR4_C3_CKE0];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_CKE0];

set_property PACKAGE_PIN G13 [get_ports DDR4_C3_CK_C1];

set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4_C3_CK_C1];

set_property PACKAGE_PIN G14 [get_ports DDR4_C3_CK_T1];

set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4_C3_CK_T1];

set_property PACKAGE_PIN L15 [get_ports DDR4_C3_CKE1];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_CKE1];

set_property PACKAGE_PIN J14 [get_ports DDR4_C3_PAR];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_PAR];

set_property PACKAGE_PIN H13 [get_ports DDR4_C3_ACT_B];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_ACT_B];

set_property PACKAGE_PIN G15 [get_ports DDR4_C3_ALERT_B];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_ALERT_B];

set_property PACKAGE_PIN D18 [get_ports DDR4_C3_EVENT_B];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_EVENT_B];

set_property PACKAGE_PIN D21 [get_ports DDR4_C3_RESET_N];

set_property IOSTANDARD LVCMOS12 [get_ports DDR4_C3_RESET_N];

set_property PACKAGE_PIN B16 [get_ports DDR4_C3_CS_B0];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_CS_B0];

set_property PACKAGE_PIN D16 [get_ports DDR4_C3_CS_B1];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_CS_B1];

set_property PACKAGE_PIN M14 [get_ports DDR4_C3_CS_B2];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_CS_B2];

set_property PACKAGE_PIN M13 [get_ports DDR4_C3_CS_B3];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_CS_B3];

set_property PACKAGE_PIN C16 [get_ports DDR4_C3_ODT0];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_ODT0];

set_property PACKAGE_PIN E16 [get_ports DDR4_C3_ODT1];

set_property IOSTANDARD SSTL12_DCI [get_ports DDR4_C3_ODT1];

set_property PACKAGE_PIN P24 [get_ports DDR4_C3_DQ0];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ0];

set_property PACKAGE_PIN N24 [get_ports DDR4_C3_DQ1];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ1];

set_property PACKAGE_PIN T24 [get_ports DDR4_C3_DQ2];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ2];

set_property PACKAGE_PIN R23 [get_ports DDR4_C3_DQ3];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ3];

set_property PACKAGE_PIN N23 [get_ports DDR4_C3_DQ4];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ4];

set_property PACKAGE_PIN P21 [get_ports DDR4_C3_DQ5];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ5];

set_property PACKAGE_PIN P23 [get_ports DDR4_C3_DQ6];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ6];

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Brand	Xilinx
Model	VCU1525
Category	Microcontrollers
Language	English

Xilinx VCU1525 User Manual

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