Xilinx Virtex-5 LXT User Manual

Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com 19
UG229 (v3.0.1) May 21, 2008
Detailed Description
R
6c. Upstream Interface Connector
The upstream interface connector (P2) is used to configure the DUT in select map or slave-
serial mode (Figure 7). This connector can be sourced by a downstream interface connector
of another prototype platform board.
X-Ref Target - Figure 7
Figure 7: Upstream Interface Connector (44-Pin Female)
UG229_07_051506
RW_B
D6
D7
DONE
CCLK
DOUT_BUSY
D1
D2
DIN
D3
D4
D5
AFX_M0
NC
NC
NC
CS_B
AFX_M1
GND
GND
GND
NC
AFX_M2
NC
GND
GND
GND
GND
GND
NC
NC
NC
NC
NC
PROG
INIT
NC
NC
NC
NC
NC
NC
NC
NC
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22
A1 A2 A3 A4 A5 A6 A7 A8 A9
A10 A11 A12
A13 A14 A15 A16 A17 A18 A19 A20 A21 A22

Xilinx Virtex-5 LXT Specifications

General

Brand	Xilinx
Model	Virtex-5 LXT
Category	Microcontrollers
Language	English