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Zynq Ultr
aScale+ V
CU TRD User Guide
20
UG1250 (v2019.1)
May
29, 2019
www
.xilinx.com
Chapt
er 2:
T
a
rgeted Referen
ce D
esig
n Deta
i
ls
PL
•
Vivado: Vivado® IP integrator d
esign that integrates the captu
re, processing
(encode/decode), and
display pipelin
e.
S
e
n
d
F
e
e
d
b
a
c
k
19
21
Table of Contents
Main Page
Default Chapter
2
Revision History
2
Table of Contents
3
Chapter 1: Introduction
5
About this TRD
5
Zynq Ultrascale+ Mpsoc Overview
7
Key Features
12
Chapter 2: Targeted Reference Design Details
16
Design Modules
16
Design Components
19
Chapter 3: APU Software Platform
21
Introduction
21
Software Architecture
22
GUI Application (Vcu_Qt)
33
Demo Mode
35
Gstreamer Application (Vcu_Gst_App)
41
Gstreamer Interface Library (Vcu_Gst_Lib)
42
AXI Performance Monitor (APM) Library (Vcu_Apm_Lib)
48
Video Library (Vcu_Video_Lib)
48
Vcu_Apm_Lib
48
Chapter 4: System Considerations
50
Boot Process
50
Chapter 5: Hardware Platform
54
Introduction
54
Clocking
56
Reset
57
Video Pipelines
58
Address Map
72
Interrupt Map
76
Appendix A: Input Configuration File
79
Descriptions
79
Appendix B: Additional Resources and Legal Notices
84
Xilinx Resources
84
Solution Centers
84
Documentation Navigator and Design Hubs
84
References
85
Please Read: Important Legal Notices
86
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