Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 43
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 3: APU Software Platform
Tab le 3 -7 describes the plug-ins used in the GStreamer interface library.
Table 3-7: GStreamer Plug-ins
Plug-in Description
v4l2src v4l2src can be used to capture video from V4L2 devices like Xilinx HDMI-RX and TPG.
Example pipeline:
gst-launch-1.0 v4l2src ! kmssink
This pipeline shows the video captured from a /dev/video0 and rendered on a display
unit.
kmssink The kmssink is a simple video sink that renders raw video frames directly in a plane of a
DRM device.
Example pipeline:
gst-launch-1.0 v4l2src ! “video/x-raw, format=NV12, width=3840,
height=2160” ! kmssink
omxh26xdec Decoder omxh26xdec is a hardware-accelerated video decoder that decodes encoded
video frames.
Example pipeline:
gst-launch-1.0 filesrc location=/media/card/abc.mp4 ! qtdemux !
h26xparse ! omxh26xdec ! kmssink
This pipeline shows an .mp4 multiplexed file where the encoded format is h26x encoded
video.
Note:
Use omxh264dec for H264 decoding and omxh265dec for H265 decoding.
omxh26xenc Encoder omxh26xenc is a hardware-accelerated video encoder that encodes raw video
frames.
Example pipeline:
gst-launch-1.0 v4l2src ! omxh26xenc ! filesink location=out.h26x
This pipeline shows the video captured from a V4L2 device that delivers raw data. The
data is encoded to the h26x encoded video type and stored to a file.
Note:
Use omxh264enc for H264 encoding and omxh265enc for H265 encoding.
alsasrc The alsasrc plug-in can be used to capture audio from audio devices like Xilinx HDMI-RX.
Example pipeline:
gst-launch-1.0 alsasrc device=hw:1,1 ! queue ! audioconvert !
audioresample ! audio/x-raw, rate=48000, channels=2, format=S24_32LE !
alsasink device="hw:1,0"
This pipeline shows the audio captured from an ALSA source and plays on an ALSA sink.
alsasink The alsasink is a simple audio sink that plays raw audio frames.
Example pipeline:
gst-launch-1.0 alsasrc device=hw:1,1 ! queue ! audioconvert !
audioresample ! audio/x-raw, rate=48000, channels=2, format=S24_32LE !
alsasink device="hw:1,0"
This pipeline shows the audio captured from the ALSA source and plays on an ALSA sink.
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Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C

Summary

Chapter 1: Introduction

About this TRD

Describes the features and functions of the Zynq UltraScale+ MPSoC VCU TRD.

Chapter 2: Targeted Reference Design Details

Design Modules

Summarizes the nine design modules (DMs) comprising the VCU TRD.

Chapter 3: APU Software Platform

Software Architecture

Shows the APU Linux software platform layers: Application, Middleware, OS, and HW.

Accelerator

VCU core supports H.264/H.265 encoding/decoding via CtrlSW, OMX IL, and GStreamer.

PCIe

Xilinx PCI Express DMA (XDMA) IP for high-performance scatter gather DMA.

Chapter 4: System Considerations

Boot Process

Describes the non-secure boot flow and SD boot mode sequence.

Global Address Map

Location of system addresses for reference.

Chapter 5: Hardware Platform

Introduction

Describes the TRD hardware architecture and ZCU106/daughter card components.

Clocking

Describes the clocking mechanism using MMCM, VCU PLL, and reference clocks.

Address Map

Address map for various IP blocks in PL for the VCU TRD.

Appendix A: Input Configuration File

Descriptions

Describes the file format of the input configuration file (input.cfg).

Appendix B: Additional Resources and Legal Notices

Documentation Navigator and Design Hubs

Access Xilinx documents, videos, and support resources.

References

Lists websites and documents providing supplemental material for the design.

Please Read: Important Legal Notices

Legal disclaimer regarding the materials and Xilinx products.