Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 49
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 3: APU Software Platform
• Enumerate entities, pads, and links
• Configure sub-devices
°
Set media bus format
°
Set dimensions (width/height)
The video_lib library sets the media bus format and video resolution on each sub-device
source and sink pad for the entire media pipeline. The formats between pads that are
connected through links need to match.
Send Feedback

Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C