Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 55
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
At a high level, the design consists of these three types of video pipelines:
• Capture/Input Pipelines
• Processing Pipelines
• Display/Output Pipelines
Capture/Input Pipelines
• The HDMI RX capture pipeline (in PL) consists of the HDMI RX Subsystem IP, Video
Processing Subsystem IP enabled for VPSS and color space conversion functionality,
and the Frame Buffer Write IP that converts the packed video data to a semi-planar
format and writes the data into memory.
• The Test Pattern Generator (TPG) capture pipeline (in PL) consists of the TPG sourcing
the live video input that goes to a Frame Buffer Write IP.
• The MIPI CSI-2 RX capture pipeline (FMC + PL) consists of an IMX274 sensor, MIPI CSI-2
Receiver Subsystem (CSI RX), the AXI4-Stream subset converter, Demosaic IP, Gamma
LUT IP, Video Processing Subsystem IP enabled for VPSS and color space conversion
functionality, and the Frame Buffer Write IP.
• The Ethernet 10G input pipeline (in PL) consists of 10G/25G Ethernet Subsystem IP that
receives video data over Ethernet and AXI DMA IP that writes it to memory.
• The SDI RX capture pipeline (in PL) consists of the SDI RX Subsystem and Video
Processing Subsystem IP enabled for VPSS and color space conversion functionality
and the Frame Buffer Write IP.
• The audio input/capture pipeline (in PL) consists of Audio Formatter IP that receives
audio input from the HDMI RX Subsystem IP and writes the data to memory.
Processing Pipelines
• The Video Codec Unit (VCU) processing pipeline (in PL) consists of the VCU IP that
contains the VCU primitive, has four 128-bit memory-mapped AXI4 interfaces coming
out, which are multiplexed for each of the encoder and decoder ports.
•
The accelerator processing pipeline (in PL) consists of a dummy accelerator that has one
128-bit memory-mapped AXI4 interface coming out, which is multiplexed with
encoder/decoder ports of the VCU.
Display/Output Pipelines
• The HDMI TX display pipeline (in PL) is controlled by the Video Mixer, which fetches
both graphics (rendered by GPU in the graphics layer) and the video layer from
memory and sends the data to the HDMI TX Subsystem. The HDMI TX Subsystem
processes data and sends it out to an external display device.
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Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C