Xilinx Zynq UltraScale+ - Page 66

Zynq UltraScale+ VCU TRD User Guide 66
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
SDI TX Display Pipeline
The SDI TX display pipeline is shown in Figure 5-9.
The SMPTE UHD-SDI Transmitter Subsystem accepts AXI4 Video streams and outputs native
SDI streams by using Xilinx transceivers as the physical layer.
The Video Mixer enables you to mix video layers and allows mixing up to four streaming or
memory layers. Each layer can be up to 4K resolution and can perform color space
conversion. The TRD design uses memory layer 1 to fetch video data.
X-Ref Target - Figure 5-9
Figure 5-9: SDI TX Display Pipeline
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SDI GT PHY SDI Tx SS Video Mixer
Rx Data AXI-Stream AXI-MM AXI-Lite
128
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128
HPM0/1
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PL PS
HP0
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Audio
Formatter
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SDI Tx Pipeline
X21034-051319
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