Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 71
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
PCIe Capture Pipeline
The design uses the PCIe Endpoint block with high-performance XDMA for data transfers
between the host system memory and the Endpoint. In the host-to-card direction, the
XDMA block moves data from the host memory to the End point Memory through PCIe.
SCD Design Pipeline
Video Scene Change is used with the Zynq UltraScale+ VCU subsystem to identify when to
update the reference frame for better performance while encoding streams. This is done
using the Video Scene Change detection IP interrupt flag. It sends fewer frames that help in
reducing the compressed stream size thereby saves bandwidth.
The Video Scene Change Detection on IP core can read up to eight video streams in
memory mode and one video stream in stream mode. In memory mode, input is read from
the memory mapped AXI4 interface. In stream mode, input is read from the AXI4-Stream
interface and output stream is same as received input stream. For more information refer to
the Video Scene Change Detection LogiCORE IP Product Guide (PG322) [Ref 23].
X-Ref Target - Figure 5-14
Figure 5-14: PCIe Capture Pipeline
X-Ref Target - Figure 5-15
Figure 5-15: SCD Pipeline
PCIe Integrated
Block
XDMA
PCIe
HP
PL
AXI-MM
PCIe Capture Pipeline
PS
128
64
128
X22776-042519
HPM0/1
HP
PL
AXI-Lite AXI-Stream AXI-MM
128
128
32
64
64
SCD Design Pipeline
PS
SCD
Frmbuf
Write
VPSS
Scaler
HDMI Rx
SS
Video
PHY
Control
X22775-051719
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Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C