Xilinx Zynq UltraScale+ - Page 78

Zynq UltraScale+ VCU TRD User Guide 78
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
VCU 94
Video Mixer 95
Table 5-9: Interrupt ID Map for SDI Design (Cont’d)
IP Core Interrupt ID
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