Yamaha CD-S700 - Schematic Diagrams

IC602
IC604
CB608
IC601
CB604
IC606
IC605
CB609
CB602
CB606
A
1
2
3
4
5
6
7
8
9
10
BCDEFGH I JK
L MN
CD-S700
39
SCHEMATIC DIAGRAMS
DIGITAL 1/2
A-1
A-2
3.3
0
3.4
2.0
2.6
2.0
2.6
3.3
2.6
0
0
0.8
0
1.9
0
0
3.3 1.7 1.7 1.7 1.8 1.8 0 0 3.2 3.2 3.2 3.2 3.3
1.6
1.6 0 1.7 1.7 3.3
1.7
1.8 0 1.9 2.0 3.3
3.2
3.2
3.3
3.4
0
3.4
0
1.9
3.4
3.4
0
0
0.8
3.4
0
3.3
0
0
0 0 0
0
1.9
0
1.7 1.7 1.7 1.7 3.2 3.2 3.3 1.7
3.3 3.3
1.8 1.8
0
1.8 1.8
3.3 1.7
1.8
0
1.7 1.5
0
0
3.3
1.9
1.7
2.4
1.7
1.7
1.7
0
7.9
1.7
3.6
3.7
3.3
4.0
7.9
1.7
3.3
3.3
0
0
0
3.5
3.7
3.7
3.6
1.5
5.8
0
1.2
3.3
1.0
1.7
0
0
1.7
3.3
1.7
0
1.9
1.9
0.2
2.4
2.0
1.8
1.3
1.8
3.3
1.2
1.3
1.7
1.7
0.9
1.5
1.5
0
1.2
1.8
1.9
1.9
1.9
1.9
1.9
1.8
1.7
3.3
3.3 1.8 1.8 1.7 1.7 1.7 3.2 3.2 3.2 1.7 1.7 1.7 1.4 3.2 3.3 0 1.7 1.8 1.8 1.8 1.8
1.7
0
0
1.6
1.5
1.6
1.6
1.7
1.7
1.7
2.0
1.9
1.8
1.6
0
3.3
3.3
1.6
1.6
0
1.3
1.7
1.7
1.7
1.7
1.7
3.4
3.43.4
1.7
0
0
0
3.3
3.3
1.7
0
1.7
3.3 1.7
0
3.3 3.3 3.3
0
3.3 3.3
1.6 1.7
0
0
3.3
0
3.3
0
3.3
3.3 3.3
3.3
0
1.6
3.3
3.3
1.6
3.3
0
CD IN
DIGITAL OUT
USB IN
AUDIO OUT
R820
J811
D803
MN6627971YA
USB
MICROPROCESSOR
CD CONTROLLER
ACTUATOR DRIVER
SDRAM
POINT A-1 XL601 (Pin 109 of IC602) POINT A-2 XL603 (Pin 12 of IC604)
VDD
A3
A2
A1
A0
A10/AP
BA
CS
RAS
CAS
WE
LDQM
DQ7
V
SSQ
DQ2
V
DDQ
DQ4
V
SSQ
DQ6
V
DDQ
DQ1
DQ5
DQ3
DQ0
VDD
VSS
A4
A5
A6
A7
A8
A9
N.C
CKE
CLK
UDQM
N.C/RFU
DQ8
V
SSQ
DQ13
V
DDQ
DQ11
V
SSQ
DQ9
V
DDQ
DQ14
DQ10
DQ12
DQ15
V
SS
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
IC605: M12L16161A-7TG
512 K x 16-bit x 2 banks synchronous DRAM
Bank Select
Data Input Register
Column Decoder
Latency & Burst Length
Programming Register
Timing Register
LWCBR
LDQM
DQi
LDQM
LWE
LCAS
LWELCBRLRAS
CLK CKE CS RAS CAS WE L(U)DQM
LCKE
LCBR
LRAS
ADD
CLK
512K x 16
512K x 16
Address Register
Row DecoderCol. Buffer
Sense AMP
Output Buffer I/O Control
Row Buffer
Refresh Counter
VIN
4
EN
1
2
5
GATE
CONTROL
UVLO
THERMAL
SHUTDOWN
CURRENT
LIMIT
FLAG
DELAY
V
OUT
3 FLG
GND
IC606: R5523N001A-TR-F
High side switch IC
IC604: MN103SFB5KYAA
USB microprocessor
TIMER
INTERRUPT
CONTROL
WDTx1
35 Factor
INTERFACE
MEMORY
8 KB
256 KByte
8 KByte
8-bit x 4
16-bit x 2
DMA 4 CH
USB
ROM
32 bit
MICRO-
PROCESSOR
CORE
FLASH
MEMORY
DATA
RAM
SIF
x 2
I2C
x 1
34 pcs (3 V type)
8 pcs (5 V type)
CLOCK &
SYSTEM control
I/O port
to OPERATION (8)_CB162
(Writing port)
To Loader ass’y
Page 41
H4
To Loader ass’y