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ZiLOG eZ80 User Manual

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eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
112
CALL cc, Mmn
Conditional CALL Subroutine
Operation
if cc {
(SP) PC
PC Mmn
}
Description
If condition
cc
is true (1), the return address is pushed onto the stack. The return address is
the address of the instruction immediately following this
CALL
instruction. The Program
Counter (PC) is loaded with the
Mmn
operand, and execution continues at the new PC
address. The
Mmn
operand is a 16- or 24-bit address, depending on the instruction suffix
and the ADL mode. Table 47 provides detailed information.
Table 47. Conditional Operations for CALL cc, Mmn Instruction
ADL Suffix Operation if condition cc is true (1)
0 None The starting Program Counter is {MBASE, PC[15:0]}.
Push a 2-byte return address, PC15:0], onto the SPS
stack. The ADL mode bit remains cleared to 0. Load a 2-
byte logical address {mm, nn} from the instruction into
PC[15:0]. The ending Program Counter is {MBASE,
PC[15:0]} = {MBASE, mm, nn}.
1 None The starting Program Counter is PC[23:0]. Push the 3-
byte return address, PC[23:0],onto the SPL stack. The
ADL mode bit remains set to 1. Load a 3-byte address
{MM, mm, nn} from the instruction into PC[23:0]. The
ending Program Counter is PC[23:0] = {MM, mm, nn}.
0 .IS The starting Program Counter is {MBASE, PC[15:0]}.
Push the 2-byte logical return address, PC[15:0], onto
the {MBASE, SPS} stack. Push a 02h byte onto the SPL
stack, indicating a call from Z80 mode (because
ADL = 0). The ADL mode bit remains cleared to 0. Load
a 2-byte logical address {mm, nn} from the instruction
into PC[15:0]. The ending Program Counter is {MBASE,
PC[15:0]}.
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ZiLOG eZ80 Specifications

General IconGeneral
CPU FamilyeZ80
CoreeZ80
Architecture8-bit
Clock Speedup to 50 MHz
Addressable Memory16 MB
Register Size8-bit
Serial InterfacesUART, SPI, I2C
Operating Temperature-40°C to +85°C
Instruction SetZ80 compatible
On-Chip Flash MemoryUp to 256 KB
On-Chip SRAMUp to 16 KB
Operating Voltage3.0V to 3.6V
Package TypesLQFP, QFP
TimersMultiple timers/counters
Power ConsumptionLow power

Summary

Introduction

Architectural Overview

Memory Modes

Z80 MEMORY Mode

Describes Z80-compatible addressing with 16-bit registers and default operating mode on reset.

ADL MEMORY Mode

Explains ADL mode utilizing 16MB linear addressing and 24-bit registers.

Registers and Bit Flags

eZ80® CPU Working Registers

Details the two banks of working registers: main and alternate.

eZ80® CPU Control Register Definitions

Lists registers controlling CPU operation: I, IX, IY, MBASE.

eZ80® CPU Registers in Z80 Mode

Details CPU registers and bit flags when operating in Z80 mode.

Memory Mode Switching

Mixed-Memory Mode Applications

Interrupts

eZ80® CPU Response to a Nonmaskable Interrupt

Details how the CPU accepts and responds to nonmaskable interrupts (NMIs).

eZ80® CPU Response to a Maskable Interrupt

Describes how the CPU responds to maskable interrupts using Interrupt Modes 0, 1, and 2.

I/O Space

Addressing Modes

CPU Instruction Set

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