EasyManuals Logo
Home>ZiLOG>Computer Hardware>eZ80

ZiLOG eZ80 User Manual

Default Icon
411 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #25 background imageLoading...
Page #25 background image
eZ80
®
CPU
User Manual
UM007714-0908 Registers and Bit Flags
16
For addition, operands with different signs never causes overflow. When adding operands
with like signs where the result yields a different sign, the overflow flag is set to 1, as indi-
cated in Table 7.
The two numbers added together result in a number that exceeds +127 and the two posi-
tive operands result in a negative number (–95), which is incorrect. Thus, the Overflow
flag is set to 1.
For subtraction, overflow can occur for operands of unlike signs. Operands of like signs
never causes overflow, as indicated in Table 8.
The minuend sign is changed from positive to negative, returning an incorrect difference.
Thus, overflow is set to 1. Another method for
predicting an overflow is to observe the carry into and out of the sign bit. If there is a carry
in and no carry out, then overflow occurs.
This flag is also used with logical operation and rotate instructions to
indicate the parity of the result. The number of 1 bits in a byte are counted. If the total is
odd, then odd parity (P = 0) is flagged. If the total is even, then even parity (P = 1) is
flagged.
During search instructions (
CPI
,
CPIR
,
CPD
,
CPDR
) and block transfer instructions
(
LDI
,
LDIR
,
LDD
,
LDDR
), the P/V flag monitors the state of the byte count register
(BC). When decrementing, the byte counter results in a 0 value and the flag is reset to 0;
otherwise the flag is logical 1.
During
LD A, I
and
LD A, R
instructions, the P/V flag is set to 1 with the contents of the
interrupt enable flip-flop (IEF2) for storage or testing. When inputting a byte from an I/O
device,
IN r,(C)
, the flag is adjusted to indicate the parity of the data.
The P/V flag is set to 1 to indicate even parity, and cleared to 0 to indicate odd parity.
Table 7. Overflow Flag Addition Settings
+120 = 0111 1000 ADDEND
+105 = 0110 1001 AUGEND
+225 1110 0001 (–95) SUM
Table 8. Overflow Flag Subtraction Settings
+127 0111 1111 MINUEND
(–) –64 1100 0000 SUBTRAHEND
+191 1011 1111 DIFFERENCE

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ZiLOG eZ80 and is the answer not in the manual?

ZiLOG eZ80 Specifications

General IconGeneral
BrandZiLOG
ModeleZ80
CategoryComputer Hardware
LanguageEnglish

Related product manuals