eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
69
MLT ss
ss[15:0]
←
ss
[15:8] X
ss
[7:0]
rr ED 4C–6C ——————
SP ED 7C
NEG
A
←
0 – A
ED 44 *** V 1*
NOP 00 ——————
OR A,s
A
←
A OR s
(HL) B6 **0 P 00
ir DD/FD B4–B5
(IX/Y+d) DD/FD B6 dd
n F6
r B0–B7
OTD2R
repeat {
({00h, DE[15:0]}
←
(HL))
BC
←
BC
–
1
DE
←
DE
–
1
HL
←
HL
–
1
} while BC
≠
0
ED BC —1—— *—
OTDM
({0000h, C})
←
(HL)
B
←
B
–
1
C
←
C
–
1
HL
←
HL
–
1
ED 8B X*X X *X
OTDMR
repeat {
({
0000h
, C})
←
(HL)
B
←
B
–
1
C
←
C
–
1
HL
←
HL
–
1
} while B
≠
0
ED 9B X1X X *X
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.
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