AR-B1479 User’s Guide
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2.4 2D GRAPHICS ENGINE
l 64-bit windows accelerator.
l Backward compatibility to SVGA standards.
l Hardware acceleration for text, bitblts, transparent blts and fills
l Up to 64 x 64 graphics hardware cursor.
l Up to 4MB long linear frame buffer.
l 8-, 16-, 24-and 32-bit pixels.
l Drivers available for various OSes.
2.5 INTERRUPT CONTROLLER
Most of the IPC signals are multiplexed: Interrupt inputs, DMA Request inputs, DMA Acknowledge outputs. The
figure below describes a complete implementation of the IRQ [15:0] time multiplexing. When an interrupts line is
used internally, the corresponding input can be grounded. In most of the embedded designs, only few interrupts
lines are necessary and the glue logic can be simplified.
Typical IRQ multiplexing
When the interface is integrated into the STPC, the corresponding interrupt line can be grounded as it is connected
internally.
For example, if the integrated IDE controller is activated, the IRQ [14] and IRQ [15] inputs can be grounded.
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