Switch S3 — Network Interface Clock Source
The D-SERV DSU/CSU can derive the Network Interface 1.544 MHz
clock in one of three ways. LOOP derives the clock from the network
input. INT derives the clock from a crystal internal to the D-SERV
DSU/CSU. DP derives the 1.544 MHz clock from the data port (tail
circuit timing application).
When the data port is configured as the clock source (tail circuit
timing) the data port input clock rate must match the data port bit rate
set with the DIP switches on S2. Selecting DP clock source also
automatically sets the Data Port Clock Source to EXTernal overriding
the INTernal setting of Switch S5-2. If another Clock Source is
selected the INTernal setting of Switch S5-2 is restored.
Switches S3-5 and S3-6 configure the Network Interface Clock Source.
NOTE: The DPLB switch position cannot be used if the
D-SERV unit is configured for data port timing (tail
circuit timing). In the event of a conflict the D-SERV
DSU/CSU will flash the front panel POWER, RED
ALARM, and DATA LEDs red.
Switch S3 — Network Interface Clock Source
Clock Source 5 6
Loop Down Down
Internal Up Down
Data Port Down Up
Loop Up Up
NOTE: The LOOP network clock source option can be
configured by setting both switches either UP or
DOWN.
Operator's Manual
17
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