Advantech PCIE-1816 - AI SCAN;CONV Clock Source

PCIE-1816_1816H User Manual 46
B.1.5 AI SCAN/CONV Clock Source
The PCIE-1816/1816H can adopt both internal and external clock sources to accom-
plish pacer acquisition. You can set the clock and trigger sources conveniently by
software. The figure can help you understand the routing route of clock and trigger
generation.
SCAN Clock
– Internal AI SCAN clock derived from 32-bit divider
– External AI SCAN clock from terminal board
– External AI CONV clock from terminal board
 Internal AI SCAN Clock
The internal AI SCAN clock uses a 100 MHz time base divided by a 32-bit divider
programmable by software. You can program SCAN clock source to internal and its
frequency the clock source as internal and the frequency, 500 KS/s maximum for the
PCIE-1816 multi-channel and 1 MS/s maximum for the PCIE-1816H multi-channel, to
activate AI conversions. To ensure system stability, SCAN clock frequency should be
less or equal to CONV clock.
 External AI SCAN Clock
The external AI SCAN clock is useful when you want to execute acquisitions at rates
not available from the internal AI SCAN clock, or when you want to pace at uneven
intervals. Acquisitions will start the rising edge of the external AI SCAN clock input.
And the frequency for PCIE-1816 and PCIE-1816H should be always limited under
500 KHz and 1 MHz. The exceeding frequency may result in data loss or unexpected
data acquisition.
 External AI CONV clock
This setting is useful when single external clock source is available. Instead of hard-
wire, the internal routing can protect signals from different line transmission delay.
CONV Clock
– Internal AI CONV clock derived from 32-bit divider
– External AI CONV clock from terminal board
 Internal AI CONV Clock
The same as internal SCAN clock, the internal AI CONV clock applies 100 MHz time
base accompanied with 32-bit divider. The maximum frequency is 500 KS/s. Accord-
ing to the sampling theory (Nyquist Theorem), you must specify a frequency that is at
least twice as fast as the input’s highest frequency component to achieve a valid
sampling. For example, to accurately sample a 20 kHz signal, you have to specify a
sampling frequency of at least 40 kHz. This consideration can avoid an error condi-
tion often know as aliasing, in which high frequency input components appear erro-
neously as lower frequencies when sampling.