Alinx AC7015 - Part 4: QSPI Flash

11 / 31
ZYNQ FPGA Development Platform AC7015 User Manual
Amazon Store: https://www.amazon.com/alinx
Sales Email: rachel.zhou@aithtech.com
DDR3_BA0
PS_DDR_BA0_502
L16
DDR3_BA1
PS_DDR_BA1_502
L17
DDR3_BA2
PS_DDR_BA2_502
M17
DDR3_S0
PS_DDR_CS_B_502
P17
DDR3_RAS
PS_DDR_RAS_B_502
R18
DDR3_CAS
PS_DDR_CAS_B_502
P20
DDR3_WE
PS_DDR_WE_B_502
R19
DDR3_ODT
PS_DDR_ODT_502
P18
DDR3_RESET
PS_DDR_DRST_B_502
F20
DDR3_CLK0_P
PS_DDR_CKP_502
N19
DDR3_CLK0_N
PS_DDR_CKN_502
N18
DDR3_CKE
PS_DDR_CKE_502
T19
Table 3-2: DDR3 DRAM Pin Assignment
Part 4: QSPI Flash
The core board is equipped with a 256MBit Quad-SPI FLASH chip, model
W25Q256FVEI, which uses the 3.3V CMOS voltage standard. Due to the non-
volatile nature of QSPI FLASH, it can be used as a boot device for the system to
store the boot image of the system. These images mainly include FPGA bit files,
ARM application code, and other user data files. The specific models and related
parameters of QSPI FLASH are shown in Table 4-1.
Position
Model
Capacity
Factory
U7
W25Q256FVEI
32M Byte
Winbond
Table 4-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS section
of the ZYNQ chip. In the system design, the GPIO port functions of these PS ports
need to be configured as the QSPI FLASH interface. Figure 4-1 shows the QSPI
Flash in the schematic.