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ZYNQ FPGA Development Platform AC7015 User Manual
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Part 13: Structure diagram
Figure 13-1: The Structure diagram (Top View)
Part 14: Connector pin definition
The core board expands four high-speed expansion ports, and uses four 80-
pin inter-board connectors (CON1~CON4) to connect with the expansion board.
The PIN pitch of the connector is 0.5mm. Among them, CON1 is connected to the
power input, the MIO signal of the PS and the JTAG signal, and CON2~CON4 are
connected to the IOs signals of BANK13, BANK34, BANK35 of PL and GTP
transceiver signal. The IOs levels of BANK35 can be changed by changing the
level of the LDO chip (U12) on the board. The default is 3.3V.
Pin assignments detailed as Table 14-1, Table 14-2, Table 14-3, Table 14-4
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