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ZYNQ FPGA Development Platform AC7015 User Manual
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Sales Email: rachel.zhou@aithtech.com
Figure 5-2: eMMC Flash on the Core Board
Pin Assignment of eMMC Flash
Table 5-2: Pin Assignment of eMMC FLASH
Part 6: Clock configuration
AC7015 core board provides active clock for PS system, PL logic part and
GTP transceiver respectively, so that PS system, PL logic and GTP transceiver
can work independently. The PS and PL terminals use a single-ended crystal, and
the GTP terminal uses a differential crystal.
PS system clock source
The ZYNQ chip provides a 33.333 MHz clock input to the PS section through
the X1 crystal on the development board. The input of the clock is connected to the
pins of PS_CLK_500 of the BANK500 of the ZYNQ chip. The schematic diagram is
shown in Figure 6-1:
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