Alstom MiCOM P545 - 4.2.5 Check sync 2 and system split (P543;P545); 4.2.6 Synchronism check (P543;P545)

P54x/EN OP/La4 Operation
(OP) 5-152 MiCOM P543, P544, P545 & P546
OP
4.2.5 Check sync 2 and system split (P543/P545)
Check Sync 2 and System Split functions are included for situations where the maximum
permitted slip frequency and phase angle for synchro check can change according to actual
system conditions. A typical application is on a closely interconnected system, where
synchronism is normally retained when a given feeder is tripped, but under some
circumstances, with parallel interconnections out of service, the feeder ends can drift out of
synchronism when the feeder is tripped. Depending on the system and machine
characteristics, the conditions for safe circuit breaker closing could be, for example:
Condition 1: for synchronized systems, with zero or very small slip:
slip 50 mHz; phase angle <30
Condition 2: for unsynchronized systems, with significant slip:
slip 250 mHz; phase angle <10 and decreasing
By enabling both Check Sync 1, set for condition 1, and Check Sync 2, set for condition 2,
the relay can be configured to allow CB closure if either of the two conditions is detected.
For manual circuit breaker closing with synchro check, some utilities might prefer to arrange
the logic to check initially for condition 1 only. However, if a System Split is detected before
the condition 1 parameters are satisfied, the relay will switch to checking for condition 2
parameters instead, based upon the assumption that a significant degree of slip must be
present when system split conditions are detected. This can be arranged by suitable PSL
logic, using the system check DDB signals.
4.2.6 Synchronism check (P54
3/P545)
Check Sync 1 and Check Sync 2 are two synchro check logic modules with similar
functionality, but independent settings.
For either module to function:
The System Checks setting must be Enabled
AND
The individual Check Sync 1(2) Status setting must be Enabled
AND
The module must be individually “enabled”, by activation of DDB signal Check Sync 1(2)
Enabled, mapped in PSL
When enabled, each logic module sets its output signal when:
Line volts and bus volts are both live (Line Live and Bus Live signals both set)
AND
Measured phase angle is < Check Sync 1(2) Phase Angle setting
AND
(For Check Sync 2 only), the phase angle magnitude is decreasing (Check Sync 1 can
operate with increasing or decreasing phase angle provided other conditions are satisfied)
AND
If Check Sync 1(2) Slip Control is set to Frequency or Frequency + Timer, the measured slip
frequency is < Check Sync 1(2) Slip Freq setting
AND
If Check Sync Voltage Blocking is set to OV, UV + OV, OV + DiffV or UV + OV + DiffV, both
line volts and bus volts magnitudes are < Check Sync Overvoltage setting
AND