Operation P54x/EN OP/La4
MiCOM P543, P544, P545 & P546
(OP) 5-171
OP
Setting
Menu text Default
Min. Max.
Step size
CB1 B Broken
0 0
25000 n^
1
Displays the total fault current interrupted by the relay for the A phase for CB1.
CB1 C Broken
0 0
25000 n^ 1n^
Displays the total fault current interrupted by the relay for the A phase for CB1.
CB1 Operate Time 0 0 0.5 s 0.001
Displays the calculated CB1 operating time.
Reset CB1 Data No Yes, No
Reset the CB1 condition counters.
CB2 A Operations 0 0 10000 1
Displays the total number of A phase trips issued by the relay for CB2.
CB2 B Operations 0 0 10000 1
Displays the total number of B phase trips issued by the relay for CB2.
CB2 C Operations 0 0 10000 1
Displays the total number of C phase trips issued by the relay for CB2.
CB2 A Broken
0 0
25000 n^
1
Displays the total fault current interrupted by the relay for the A phase for CB2.
CB2 B Broken
0 0
25000 n^
1
Displays the total fault current interrupted by the relay for the A phase for CB2.
CB2 C Broken
0 0
25000 n^ 1n^
Displays the total fault current interrupted by the relay for the A phase for CB2.
CB2 Operate Time 0 0 0.5 s 0.001
Displays the calculated CB2 operating time.
Reset CB2 Data No Yes, No
Reset the CB2 condition counters.
The counters above may be reset to zero for example, following a maintenance inspection
and overhaul. The circuit breaker condition monitoring counters will be updated every time
the relay issues a trip command. In cases where the breaker is tripped by an external
protection device it is also possible to update the circuit breaker condition monitoring data.
This is achieved by allocating one of the P544/P546 opto-isolated inputs (via the
programmable scheme logic) to accept a trigger from an external device. The signal that is
mapped to the opto is called ‘External Trip’.
Note: When in ‘commissioning test mode’ the circuit breaker condition
monitoring counters will not be updated.
The measurement of circuit breaker broken current, operating time and the overall circuit
breaker monitoring logic diagram, are shown in Figure 109, Figure 110, Figure 111,
Figure 112, Figure 113 and Figure 114.
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