Altera DE2 Board - Page 40

Using the System
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SRAM_DQ[2] PIN_AF6 SRAM Data[2]
SRAM_DQ[3] PIN_AA9 SRAM Data[3]
SRAM_DQ[4] PIN_AA10 SRAM Data[4]
SRAM_DQ[5] PIN_AB10 SRAM Data[5]
SRAM_DQ[6] PIN_AA11 SRAM Data[6]
SRAM_DQ[7] PIN_Y11 SRAM Data[7]
SRAM_DQ[8] PIN_AE7 SRAM Data[8]
SRAM_DQ[9] PIN_AF7 SRAM Data[9]
SRAM_DQ[10] PIN_AE8 SRAM Data[10]
SRAM_DQ[11] PIN_AF8 SRAM Data[11]
SRAM_DQ[12] PIN_W11 SRAM Data[12]
SRAM_DQ[13] PIN_W12 SRAM Data[13]
SRAM_DQ[14] PIN_AC9 SRAM Data[14]
SRAM_DQ[15] PIN_AC10 SRAM Data[15]
SRAM_WE_N PIN_AE10 SRAM Write Enable
SRAM_OE_N PIN_AD10 SRAM Output Enable
SRAM_UB_N PIN_AF9 SRAM High-byte Data Mask
SRAM_LB_N PIN_AE9 SRAM Low-byte Data Mask
SRAM_CE_N PIN_AC11 SRAM Chip Enable
Table 3.16 Pin Assignment for SRAM
Signal Name FPGA Pin No.
Description
FL_ADDR[0] PIN_AC18 FLASH Address[0]
FL_ADDR[1] PIN_AB18 FLASH Address[1]
FL_ADDR[2] PIN_AE19 FLASH Address[2]
FL_ADDR[3] PIN_AF19 FLASH Address[3]
FL_ADDR[4] PIN_AE18 FLASH Address[4]
FL_ADDR[5] PIN_AF18 FLASH Address[5]
FL_ADDR[6] PIN_Y16 FLASH Address[6]
FL_ADDR[7] PIN_AA16 FLASH Address[7]
FL_ADDR[8] PIN_AD17 FLASH Address[8]
FL_ADDR[9] PIN_AC17 FLASH Address[9]
FL_ADDR[10] PIN_AE17 FLASH Address[10]
FL_ADDR[11] PIN_AF17 FLASH Address[11]
FL_ADDR[12] PIN_W16 FLASH Address[12]
FL_ADDR[13] PIN_W15 FLASH Address[13]
FL_ADDR[14] PIN_AC16 FLASH Address[14]