AT90S4414/8515
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Bit 0 - EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the
EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the
EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE
has been set, the CPU is halted for two cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or
address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.
Prevent EEPROM Corruption
During periods of low V
CC,
the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the
EEPROM to operate properly. These issues are the same as for board level systems using the EEPROM, and the same
design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence
to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incor-
rectly, if the supply voltage for executing instructions is too low.
EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This is best done by an exter-
nal low V
CC
Reset Protection circuit, often referred to as a Brown-Out Detector (BOD). Please refer to application
note AVR 180 for design considerations regarding power-on reset and low voltage detection.
2. Keep the AVR core in Power Down Sleep Mode during periods of low V
CC
. This will prevent the CPU from attempting
to decode and execute instructions, effectively protecting the EEPROM registers from unintentional writes.
3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash
memory can not be updated by the CPU, and will not be subject to corruption.
Serial Peripheral Interface - SPI
The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and
peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following:
• Full-duplex, 3-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Four Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wakeup from Idle Mode (Slave Mode Only)
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