AT90S4414/8515
38
Watchdog Timer
The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1MHz. This is the typical value at V
CC
=
5V. See characterization data for typical values at other V
CC
levels. By controlling the Watchdog Timer prescaler, the
Watchdog reset interval can be adjusted, see Table 15 for a detailed description. The WDR - Watchdog Reset - instruction
resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog reset, the AT90S4414/8515 resets and executes from the reset vector. For timing
details on the Watchdog reset, refer to page 23.
To prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is
disabled. Refer to the description of the Watchdog Timer Control Register for details.
Figure 33. Watchdog Timer
Watchdog Timer Control Register - WDTCR
•
Bits 7..5 - Res: Reserved bits
These bits are reserved bits in the AT90S4414/8515 and will always read as zero.
•
Bit 4 - WDTOE: Watch Dog Turn-Off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware
will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.
•
Bit 3 - WDE: Watch Dog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function
is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following
procedure must be followed:
1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though
it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog.
Bit 76543210
$21 ($41) - - - WDTOE WDE WDP2 WDP1 WDP0 WDTCR
Read/Write R R R R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
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