AT90S4414/8515
37
Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are transferred to a temporary loca-
tion. They are latched when Timer/Counter1 reaches the value TOP. This prevents the occurrence of odd-length PWM
pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B write. See Figure 32 for an example.
Figure 32. Effects on Unsynchronized OCR1 Latching
During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the
temporary location. This means that the most recently written value always will read out of OCR1A/B
When the OCR1 contains $0000 or TOP, the output OC1A/OC1B is updated to low or high on the next compare match
according to the settings of COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table .
Note: X = A or B
In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from $0000. Timer Overflow Interrupt1
operates exactly as in normal Timer/Counter mode, i.e. it is executed when TOV1 is set provided that Timer Overflow
Interrupt1 and global interrupts are enabled. This does also apply to the Timer Output Compare1 flags and interrupts.
Table 14. PWM Outputs OCR1X = $0000 or TOP
COM1X1 COM1X0 OCR1X Output OC1X
1 0 $0000 L
10TOP H
1 1 $0000 H
11TOP L
Counter
V
alue
Compare V
alue
PWM
Output OC1X
Synchronized OCR1X Latch
Counter
Value
Compare Value
PWM Output OC1X
Unsynchronized OCR1X Latch
Glitch
Compare Value changes
Note: X = A or B
Compare V
alue changes
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