Atmel AT90S8515-8PI - Page 54

AT90S4414/8515
54
Figure 42. External SRAM Connected to the AVR
Figure 43. External Data SRAM Memory Cycles without Wait State
Figure 44. External Data SRAM Memory Cycles with Wait State
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
DQ
G
Port A
ALE
Port C
RD
WR
AVR
System Clock Ø
ALE
WR
RD
Data / Address [7..0]
Data / Address [7..0]
Address [15..8]
Address
Address
Address
T1 T2 T3
Prev. Address
Prev. Address
Prev. Address
Data
Data
WriteRead
Address
Address
System Clock Ø
ALE
WR
RD
Data / Address [7..0]
Data / Address [7..0]
Address [15..8]
Address
Address
Address
T1 T2 T3 T4
Prev. Address
Prev. Address
Prev. Address
Data
Data
WriteRead
Addr.
Addr.