Atmel AT90S8515-8PI - Page 61

AT90S4414/8515
61
Figure 50. Port B Schematic Diagram (Pin PB6)
Figure 51. Port B Schematic Diagram (Pin PB7)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB6
R
R
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
DDB6
PORTB6
SPE
MSTR
SPI SLAVE
OUT
SPI MASTER
IN
RL
RP
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB7
R
R
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
DDB7
PORTB7
SPE
MSTR
SPI CLOCK
OUT
SPI CLOCK
IN
RL
RP